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The problem that the PS side does not close the cache when ZYNQ debugs DDR [Copy link]

The PL side writes data to DDR via AXI-FULL. The PS side cannot see the data changes using the memory monitoring window. However, when the scroll bar is scrolled down, the data updated by the PL side will be displayed again, and the data displayed in the memory monitoring window is gray (Figure 1).

Later, I found that it was because the cache was turned on on the PS side. After turning off the cache using Xil_DCacheDisable();, the data was normal (Figure 2).

This post is from FPGA/CPLD
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