Regarding the power supply design part of DDR, it is worth collecting!

Generally speaking, in the DDR hardware circuit design process, there are unreasonable parts about the DDR power supply design. Here is a brief introduction to the DDR power supply:

DDR power supplies can be divided into three categories:

(1) Main power supply VDD and VDDQ

The main power supply requirement is VDDQ=VDD. VDDQ is the power supply for the IO buffer, and VDD is the power supply. However, in general use, VDDQ and VDD are combined into one power supply. Some chips also have VDDL, which supplies power to the DLL. It can also use the same power supply as VDD.

When designing a power supply, you need to consider whether the voltage and current meet the requirements, the power-on sequence and power-on time of the power supply, monotonicity, etc.

The power supply voltage requirements are generally within ±5%.

The current needs to be calculated based on the different chips used and the number of chips. Since the current of DDR is generally relatively large, when designing the PCB, it is the most ideal state to have a complete power plane laid on the pins, and increase capacitor energy storage at the power inlet, and add a 10nF~100nF small capacitor filtering.

(2) Reference power supply Vref

Vref is the reference voltage, which needs to be accurate and constant, and is used as the basis for judging the high and low levels of signals.

All DDR signals are actually differential signals, which are relative to Vref, so they are also differential signals. For more details, see the chapter about DDR in "High-speed Circuit Design Practice".

The reference power supply Vref is required to follow VDDQ, and Vref=VDDQ/2, so it can be provided by a power chip, or it can be obtained by resistor voltage division. Since Vref generally has a small current, on the order of several mA to dozens of mA, the resistor voltage divider method is used to save costs and be more flexible in layout. It is placed closer to the Vref pin and follows closely. VDDQ voltage, so it is recommended to use this method. It should be noted that the resistor used for voltage division can be between 100 and 10K, and a resistor with a precision of 1% is required.

Each pin of the Vref reference voltage needs to be filtered with a 10nF capacitor, and it is better to connect a capacitor in parallel with each voltage dividing resistor.

Vref is divided into Vrefca and Vrefdq:

Vrefca Supply Reference voltage for control, command, and address: Vrefca must be

maintained at all times (including self refresh) for proper device operation.

Vrefdq Supply Reference voltage for data: Vrefdq must be maintained at all times (excluding self

refresh) for proper device operation.

Below is a screenshot of the FSL i.MX6 design:

Maintain at least a 20–25 mil clearance from V REF to other traces; if possible, isolate VREF with adjacent

ground traces.(nxp-fsl design guide)

(3)VTT (Tracking Termination Voltage) used for matching

VTT, the power supply used for pull-up and pull-down resistors, has large current, large fluctuations, and large noise.

VTT is the power supply that the matching resistor is pulled up to, VTT=VDDQ/2. In the design of DDR, depending on the topology, some designs cannot use VTT, such as when the controller has relatively few DDR devices. If VTT is used, the current requirement of VTT is relatively large, so the traces need to be laid with copper sheets. And VTT requires that the power supply can both provide current and sink (sink) current.

Under normal circumstances, you can use a VTT-generating power chip specially designed for DDR to meet the requirements (I have used a simple linear regulator in the past and no problems were found. This method is still not recommended!).

Moreover, a 10nF~100nF capacitor is generally placed next to each resistor pulled to VTT. The entire VTT circuit requires a uF-level large capacitor for energy storage.

Under normal circumstances, DDR data lines have a one-drive-one topology, and DDR2 and DDR3 have ODT internal matching, so there is no need to pull VTT for matching to get better signal quality. If the address and control signal lines have multiple loads, there will be one drive for multiple loads, and there is no ODT inside. The topology is a T-point structure, so VTT is often needed to control signal quality matching.