How to pair MCU with FPGA to improve system efficiency?

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How to pair MCU with FPGA to improve system efficiency? [Copy link]

FPGAs have become so cost-effective that they are increasingly used in conjunction with MCUs to improve overall system efficiency. Uses include adding extra functionality to a given board space, adding energy-efficient processing to the front end of a complex algorithm, aggregating multiple external devices to offload a high-performance MCU, or acting as the "glue" logic needed to adapt an existing design to a new interface requirement. FPGAs offer additional flexibility that is often lacking in standard MCUs . This article will quickly review a few applications where FPGAs and MCUs have been "paired" to show how system efficiency can be improved significantly by reducing power consumption, reducing board space, increasing processing performance, or interface flexibility.

FPGAs as MCU Companion Devices
How often have you chosen an MCU for your design that didn't quite have all the interface channels you needed? Perhaps your initial choice of MCU was a good fit, but new requirements have arisen because your customers need to add some additional interfaces to their designs. You might be able to use a more complex MCU, but this would likely add significant board space (because it's only available in a high-pin-count package), increased power (because it only offers more flash and SRAM than you really need ), or higher cost (for the two reasons mentioned above).

One way to address this dilemma is to plan for the need for additional interfaces by adding an FPGA alongside the MCU. FPGAs can easily provide additional interfaces, providing only the ones you need while limiting the increase in board space, cost, and power consumption. In fact, compared to the option of using a more complex MCU, it often reduces board space, reduces cost, and reduces power consumption.

For example, ultra-low power FPGAs can provide up to 26 signal IOs in a very small 2.078 mm × 2.078 mm board footprint, and because these devices are configured through on-chip NVM, you do not need additional board space for configuring the device. These FPGAs also have two dedicated I2C interfaces and two dedicated SPI interfaces with a lot of configurable logic to add more interfaces as the application needs (until you run out of pins).

The device also has up to 80kbits of embedded block RAM that can be used for interface FIFOs and buffers, so the MCU can wait until the entire data packet is ready for processing. The DSP module can also be used to perform low-level data processing on the raw sensor data as a pre-processing step before sending the data to the MCU. When the FPGA can intelligently aggregate the data before interrupting the MCU, MCU power consumption can be greatly reduced.

Quick response to FPGA interface requests
When using FPGA companion devices, it is very important to respond quickly to the FPGA's service requests. For example, an audio interface may need to have higher priority access than sensor data because "pauses" in the audio data must be avoided or the user experience may be significantly degraded. Often being able to support a variety of interrupt priorities helps improve the usefulness of the FPGA partner and further improve overall system performance and power efficiency.

Effective use of DMA also helps to further offload the MCU and improve efficiency. For example, the FPGA may first buffer a complete packet of pre-processed raw data to reduce the size of the message that needs to be stored and transmitted. The FPGA can interrupt the MCU and start a DMA transfer to move the entire message into the MCU memory. Once the DMA transfer is complete and the entire message is ready for processing, the CPU can be interrupted and processing of the message can begin.

For example, a 32-bit MCU has a DMA controller and an interrupt controller, both of which are programmable priorities. The interrupt controller has a priority block on the right that generates interrupt levels for the CPU. The priority block selects interrupts with a priority, defined by the interrupt level field in the interrupt priority register (IPRn) associated with each interrupt source. Therefore, a higher priority source (such as a real-time audio interface) can be assigned a higher priority than a low-frequency sensor on the I2C port to ensure faster processing.

annysky2012

Thanks for sharing~~

freebsder

Thanks for sharing!