TI official header file DSP2833x_Gpio.h content

fish001

TI official header file DSP2833x_Gpio.h content [Copy link]

The contents of TI's official header file DSP2833x_Gpio.h are as follows:

// TI File $Revision: /main/4 $
// Checkin $Date: November 15, 2007 09:58:53 $
//#################################################################################
//
// FILE: DSP2833x_Gpio.h
//
// TITLE: DSP2833x general application I/O definitions.
//
//#############################################################################################
// $TI Release: DSP2833x/DSP2823x C/C++ Header Files V1.31 $
// $Release Date: August 4, 2009 $
//###################################################################

#ifndef DSP2833x_GPIO_H
#define DSP2833x_GPIO_H

#ifdef __cplusplus
extern "C" {
#endif

//----------------------------------------------------
// GPIO A control register bit definition*/
struct GPACTRL_BITS { // bits description
Uint16 QUALPRD0:8; // 7:0 sampling period
Uint16 QUALPRD1:8; // 15:8 sampling period
Uint16 QUALPRD2:8; // 23:16 sampling period
Uint16 QUALPRD3:8; // 31:24 sampling period
};
//GPIO A control register
union GPACTRL_REG {
Uint32 all;
struct GPACTRL_BITS bit; //GPIO A control register bit definition
};

//----------------------------------------------------
// GPIO B control register bit definition*/
struct GPBCTRL_BITS { // bits description
Uint16 QUALPRD0:8; // 7:0 sampling period
Uint16 QUALPRD1:8; // 15:8 sampling period
Uint16 QUALPRD2:8; // 23:16 sampling period
Uint16 QUALPRD3:8; // 31:24 sampling period
};
//GPIO B control register
union GPBCTRL_REG {
Uint32 all;
struct GPBCTRL_BITS bit; //GPIO B control register bit definition
};

//----------------------------------------------------
// GPIO A Qual/MUX select register bit definitions */
struct GPA1_BITS { // bits description
Uint16 GPIO0:2; // 1:0 GPIO0
Uint16 GPIO1:2; // 3:2 GPIO1
Uint16 GPIO2:2; // 5:4 GPIO2
Uint16 GPIO3:2; // 7:6 GPIO3
Uint16 GPIO4:2; // 9:8 GPIO4
Uint16 GPIO5:2; // 11:10 GPIO5
Uint16 GPIO6:2; // 13:12 GPIO6
Uint16 GPIO7:2; // 15:14 GPIO7
Uint16 GPIO8:2; // 17:16 GPIO8
Uint16 GPIO9:2; // 19:18 GPIO9
Uint16 GPIO10:2; // 21:20 GPIO10
Uint16 GPIO11:2; // 23:22 GPIO11
Uint16 GPIO12:2; // 25:24 GPIO12
Uint16 GPIO13:2; // 27:26 GPIO13 Uint16 GPIO14
:2; // 29:28 GPIO14
Uint16 GPIO15:2; // 31:30 GPIO15
};

struct GPA2_BITS { // bits 描述
Uint16 GPIO16:2; // 1:0 GPIO16
Uint16 GPIO17:2; // 3:2 GPIO17
Uint16 GPIO18:2; // 5:4 GPIO18
Uint16 GPIO19:2; // 7:6 GPIO19
Uint16 GPIO20:2; // 9:8 GPIO20
Uint16 GPIO21:2; // 11:10 GPIO21
Uint16 GPIO22:2; // 13:12 GPIO22
Uint16 GPIO23:2; // 15:14 GPIO23
Uint16 GPIO24:2; // 17:16 GPIO24
Uint16 GPIO25:2; // 19:18 GPIO25
Uint16 GPIO26:2; // 21:20 GPIO26
Uint16 GPIO27:2; // 23:22 GPIO27
Uint16 GPIO28:2; // 25:24 GPIO28
Uint16 GPIO29:2; // 27:26 GPIO29
Uint16 GPIO30:2; // 29:28 GPIO30
Uint16 GPIO31:2; // 31:30 GPIO31
};
// GPIO B Qual/MUX 选择寄存器位定义 */
struct GPB1_BITS { // bits 描述
Uint16 GPIO32:2; // 1:0 GPIO32
Uint16 GPIO33:2; // 3:2 GPIO33
Uint16 GPIO34:2; // 5:4 GPIO34
Uint16 GPIO35:2; // 7:6 GPIO35
Uint16 GPIO36:2; // 9:8 GPIO36
Uint16 GPIO37:2; // 11:10 GPIO37
Uint16 GPIO38:2; // 13:12 GPIO38
Uint16 GPIO39:2; // 15:14 GPIO39
Uint16 GPIO40:2; // 17:16 GPIO40
Uint16 GPIO41:2; // 19:16 GPIO41
Uint16 GPIO42:2; // 21:20 GPIO42
Uint16 GPIO43:2; // 23:22 GPIO43
Uint16 GPIO44:2; // 25:24 GPIO44
Uint16 GPIO45:2; // 27:26 GPIO45
Uint16 GPIO46:2; // 29:28 GPIO46
Uint16 GPIO47:2; // 31:30 GPIO47
};

struct GPB2_BITS { // bits 描述
Uint16 GPIO48:2; // 1:0 GPIO48
Uint16 GPIO49:2; // 3:2 GPIO49
Uint16 GPIO50:2; // 5:4 GPIO50
Uint16 GPIO51:2; // 7:6 GPIO51
Uint16 GPIO52:2; // 9:8 GPIO52
Uint16 GPIO53:2; // 11:10 GPIO53
Uint16 GPIO54:2; // 13:12 GPIO54
Uint16 GPIO55:2; // 15:14 GPIO55
Uint16 GPIO56:2; // 17:16 GPIO56
Uint16 GPIO57:2; // 19:18 GPIO57
Uint16 GPIO58:2; // 21:20 GPIO58
Uint16 GPIO59:2; // 23:22 GPIO59
Uint16 GPIO60:2; // 25:24 GPIO60
Uint16 GPIO61:2; // 27:26 GPIO61
Uint16 GPIO62:2; // 29:28 GPIO62
Uint16 GPIO63:2; // 31:30 GPIO63
};
// GPIO C Qual/MUX 选择寄存器位定义 */
struct GPC1_BITS { // bits 描述
Uint16 GPIO64:2; // 1:0 GPIO64
Uint16 GPIO65:2; // 3:2 GPIO65
Uint16 GPIO66:2; // 5:4 GPIO66
Uint16 GPIO67:2; // 7:6 GPIO67
Uint16 GPIO68:2; // 9:8 GPIO68
Uint16 GPIO69:2; // 11:10 GPIO69
Uint16 GPIO70:2; // 13:12 GPIO70
Uint16 GPIO71:2; // 15:14 GPIO71
Uint16 GPIO72:2; // 17:16 GPIO72
Uint16 GPIO73:2; // 19:18 GPIO73
Uint16 GPIO74:2; // 21:20 GPIO74
Uint16 GPIO75:2; // 23:22 GPIO75
Uint16 GPIO76:2; // 25:24 GPIO76
Uint16 GPIO77:2; // 27:26 GPIO77
Uint16 GPIO78:2; // 29:28 GPIO78
Uint16 GPIO79:2; // 31:30 GPIO79
};

struct GPC2_BITS { // bits description
Uint16 GPIO80:2; // 1:0 GPIO80
Uint16 GPIO81:2; // 3:2 GPIO81
Uint16 GPIO82:2; // 5:4 GPIO82
Uint16 GPIO83:2; // 7:6 GPIO83
Uint16 GPIO84:2; // 9:8 GPIO84
Uint16 GPIO85:2; // 11:10 GPIO85
Uint16 GPIO86:2; // 13:12 GPIO86
Uint16 GPIO87:2; // 15:14 GPIO87
Uint16 rsvd:16; // 31:16 reserved
};

//GPIO A Qual/MUX select register*/
union GPA1_REG {
Uint32 all;
struct GPA1_BITS bit;
};

union GPA2_REG {
Uint32 all;
struct GPA2_BITS bit;
};
// GPIO B Qual/MUX select register*/
union GPB1_REG {
Uint32 all;
struct GPB1_BITS bit;
};

union GPB2_REG {
Uint32 all;
struct GPB2_BITS bit;
};
// GPIO C Qual/MUX selection register*/
union GPC1_REG {
Uint32 all;
struct GPC1_BITS bit;
};

union GPC2_REG {
Uint32 all;
struct GPC2_BITS bit;
};

//----------------------------------------------------
// GPIO A DIR/TOGGLE/SET/CLEAR register bit definition*/
struct GPADAT_BITS { // bits description
Uint16 GPIO0:1; // 0 GPIO0
Uint16 GPIO1:1; // 1 GPIO1
Uint16 GPIO2:1; // 2 GPIO2
Uint16 GPIO3:1; // 3 GPIO3
Uint16 GPIO4:1; // 4 GPIO4
Uint16 GPIO5:1; // 5 GPIO5
Uint16 GPIO6:1; // 6 GPIO6
Uint16 GPIO7:1; // 7 GPIO7
Uint16 GPIO8:1; // 8 GPIO8
Uint16 GPIO9:1; // 9 GPIO9
Uint16 GPIO10:1; // 10 GPIO10
Uint16 GPIO11:1; // 11 GPIO11
Uint16 GPIO12:1; // 12 GPIO12
Uint16 GPIO13:1; // 13 GPIO13
Uint16 GPIO14:1; // 14 GPIO14 Uint16
GPIO15:1; // 15 GPIO15
Uint16 GPIO16:1; // 16 GPIO16
Uint16 GPIO17: 1; // 17 GPIO17
Uint16 GPIO18:1; // 18 GPIO18
Uint16 GPIO19:1; // 19 GPIO19
Uint16 GPIO20:1; // 20 GPIO20
Uint16 GPIO21:1; // 21 GPIO21
Uint16 GPIO22:1; //
1 ; // 31 GPIO31 }; //
GPIO B DIR/TOGGLE/
SET / CLEAR register bit definition*/ struct GPBDAT_BITS { // bits description Uint16 GPIO32:1; // 0 GPIO32 Uint16 GPIO33:1; // 1 GPIO33 Uint16 GPIO34:1; // 2 GPIO34 Uint16 GPIO35:1; // 3 GPIO35 Uint16 GPIO36:1; // 4 GPIO36 Uint16 GPIO37:1; // 5 GPIO37 Uint16 GPIO38:1; // 6 GPIO38 U int16 GPIO39:1; // 7 GPIO39 Uint16 GPIO40:1; // 8 GPIO40 Uint16 GPIO41:1; // 9 GPIO41 Uint16 GPIO42:1; // 10 GPIO42 Uint16 GPIO43:1; // 11 GPIO43 Uint16 GPIO44:1; // 12 GPIO44






















Uint16 GPIO45:1; // 13 GPIO45
Uint16 GPIO46:1; // 14 GPIO46
Uint16 GPIO47:1; // 15 GPIO47
Uint16 GPIO48:1; // 16 GPIO48
Uint16 GPIO49:1; // 17 GPIO49
Uint16 GPIO50:1; // 18 GPIO50
Uint16 GPIO51:1; // 19 GPIO51
Uint16 GPIO52:1; // 20 GPIO52
Uint16 GPIO53:1; // 21 GPIO53
Uint16 GPIO54:1; // 22 GPIO54
Uint16 GPIO55:1; // 23 GPIO55
Uint16 GPIO56:1; // 24 GPIO56
Uint16 GPIO57:1; // 25 GPIO57
Uint16 GPIO58:1; // 26 GPIO58
Uint16 GPIO59:1; // 27 GPIO59
Uint16 GPIO60:1; // 28 GPIO60
Uint16 GPIO61:1; // 29 GPIO61
Uint16 GPIO62:1; // 30 GPIO62
Uint16 GPIO63:1; // 31 GPIO63
};
// GPIO C DIR/TOGGLE/SET/CLEAR 寄存器位定义 */
struct GPCDAT_BITS { // bits 描述
Uint16 GPIO64:1; // 0 GPIO64
Uint16 GPIO65:1; // 1 GPIO65
Uint16 GPIO66:1; // 2 GPIO66
Uint16 GPIO67:1; // 3 GPIO67
Uint16 GPIO68:1; // 4 GPIO68
Uint16 GPIO69:1; // 5 GPIO69
Uint16 GPIO70:1; // 6 GPIO70
Uint16 GPIO71:1; // 7 GPIO71
Uint16 GPIO72:1; // 8 GPIO72
Uint16 GPIO73:1; // 9 GPIO73
Uint16 GPIO74:1; // 10 GPIO74
Uint16 GPIO75:1; // 11 GPIO75
Uint16 GPIO76:1; // 12 GPIO76
Uint16 GPIO77:1; // 13 GPIO77
Uint16 GPIO78:1; // 14 GPIO78
Uint16 GPIO79:1; // 15 GPIO79
Uint16 GPIO80:1; // 16 GPIO80
Uint16 GPIO81:1; // 17 GPIO81
Uint16 GPIO82:1; // 18 GPIO82
Uint16 GPIO83:1; // 19 GPIO83
Uint16 GPIO84:1; // 20 GPIO84
Uint16 GPIO85:1; // 21 GPIO85
Uint16 GPIO86:1; // 22 GPIO86
Uint16 GPIO87:1; // 23 GPIO87
Uint16 rsvd1:8; // 31:24 reserved
};

// GPIO A DIR/TOGGLE/SET/CLEAR 寄存器 */
union GPADAT_REG {
Uint32 all;
struct GPADAT_BITS bit;
};
// GPIO B DIR/TOGGLE/SET/CLEAR 寄存器 */
union GPBDAT_REG {
Uint32 all;
struct GPBDAT_BITS bit;
};
// GPIO C DIR/TOGGLE/SET/CLEAR 寄存器 */
union GPCDAT_REG {
Uint32 all;
struct GPCDAT_BITS bit;
};

//----------------------------------------------------
// GPIO Xint1/XINT2/XNMI selection register bit definition*/
struct GPIOXINT_BITS { // bits description
Uint16 GPIOSEL:5; // 4:0 Select GPIO interrupt input source
Uint16 rsvd1:11; // 15:5 reserved
};
// GPIO Xint1/XINT2/XNMI selection register*/
union GPIOXINT_REG {
Uint16 all;
struct GPIOXINT_BITS bit;
};

//GPIO Control Registersstruct
GPIO_CTRL_REGS {
union GPACTRL_REG GPACTRL; // GPIO A Control Register (GPIO0 to 31)
union GPA1_REG GPAQSEL1; // GPIO A Select Input Limit 1 (GPIO0 to 15)
union GPA2_REG GPAQSEL2; // GPIO A Select Input Limit 2 (GPIO16 to 31)
union GPA1_REG GPAMUX1; // GPIO A Select Register 1 (GPIO0 to 15)
union GPA2_REG GPAMUX2; // GPIO A Select Register 2 (GPIO16 to 31)
union GPADAT_REG GPADIR; // GPIO A Input Output Direction (GPIO0 to 31)
union GPADAT_REG GPAPUD; // GPIO A Pull-up Disable Register (GPIO0 to 31)
Uint32 rsvd1; // reserved
union GPBCTRL_REG GPBCTRL; // GPIO B Control Register (GPIO32 to 63)
union GPB1_REG GPBQSEL1; // GPIO B Select Input Limit 1 (GPIO32 to 47)
union GPB2_REG GPBQSEL2; // GPIO B Select Input Limit 2 (GPIO48 to 63)
union GPB1_REG GPBMUX1; // GPIO B Select Register 1 (GPIO32 to 47)
union GPB2_REG GPBMUX2; // GPIO B Select Register 2 (GPIO48 to 63)
union GPBDAT_REG GPBDIR; // GPIO B Input Output Direction (GPIO32 to 63)
union GPBDAT_REG GPBPUD; // GPIO B Pull-up Disable Register (GPIO32 to 63)
Uint16 rsvd2[8]
; GPC1_REG GPCMUX1; // GPIO C Select Register 1 (GPIO64 to 79)
union GPC2_REG GPCMUX2; // GPIO C Select Register 2 (GPIO80 to 95)
union GPCDAT_REG GPCDIR; // GPIO C Input Output Direction (GPIO64 to 95)
union GPCDAT_REG GPCPUD; // GPIO C Pull-up Disable Register (GPIO64 to 95)
};
//GPIO Control Registersstruct
GPIO_DATA_REGS {
union GPADAT_REG GPADAT; // GPIO Data Register (GPIO0 to 31)
union GPADAT_REG GPASET; // GPIO Set Data Register (GPIO0 to 31)
union GPADAT_REG GPACLEAR; // GPIO Clear Data Register (GPIO0 to 31)
union GPADAT_REG GPATOGGLE; // GPIO data toggle register (GPIO0 to 31)
union GPBDAT_REG GPBDAT; // GPIO data register (GPIO32 to 63)
union GPBDAT_REG GPBSET; // GPIO set data register (GPIO32 to 63)
union GPBDAT_REG GPBCLEAR; // GPIO clear data register (GPIO32 to 63)
union GPBDAT_REG GPBTOGGLE; // GPIO data toggle register (GPIO32 to 63)
union GPCDAT_REG GPCDAT; // GPIO data register (GPIO64 to 95)
union GPCDAT_REG GPCSET; // GPIO set data register (GPIO64 to 95)
union GPCDAT_REG GPCCLEAR; // GPIO clear data register (GPIO64 to 95)
union GPCDAT_REG GPCTOGGLE; // GPIO data toggle register (GPIO64 to 95)
Uint16 rsvd1[8];
};
//GPIO interrupt register
struct GPIO_INT_REGS {
union GPIOXINT_REG GPIOXINT1SEL; // XINT1 GPIO input selection
union GPIOXINT_REG GPIOXINT2SEL; // XINT2 GPIO input selection
union GPIOXINT_REG GPIOXNMISEL; // XNMI_Xint13 GPIO input select
union GPIOXINT_REG GPIOXINT3SEL; // XINT3 GPIO input select
union GPIOXINT_REG GPIOXINT4SEL; // XINT4 GPIO input select
union GPIOXINT_REG GPIOXINT5SEL; // XINT5 GPIO input select
union GPIOXINT_REG GPIOXINT6SEL; // XINT6 GPIO input select
union GPIOXINT_REG GPIOXINT7SEL; // XINT7 GPIO input select
union GPADAT_REG GPIOLPMSEL; // Wake-up low power mode source select register
};

//---------------------------------------------------------------------------
// GPI/O external reference and function declaration:
//
extern volatile struct GPIO_CTRL_REGS GpioCtrlRegs;
extern volatile struct GPIO_DATA_REGS GpioDataRegs;
extern volatile struct GPIO_INT_REGS GpioIntRegs;

#ifdef __cplusplus
}
#endif /* extern "C" */

#endif // end of DSP2833x_GPIO_H definition

//=================================================================================
// End of file.
//=

...

// TI File $Revision: /main/1 $
// Checkin $Date: August 18, 2006 13:46:25 $
//##################################################################################
//
// FILE: DSP2833x_Gpio.c
//
// TITLE: DSP2833x general purpose I/O initialization & support functions.
//
//############################################################################################
// $TI Release: DSP2833x Header Files V1.01 $
// $Release Date: September 26, 2007 $
//######################################################################

#include "DSP2833x_Device.h" // DSP2833x Headerfile Include File
#include "DSP2833x_Examples.h" // DSP2833x Examples Include File

//---------------------------------------------------------------------------
// InitGpio:
//---------------------------------------------------------------------------
// This function initializes to a known (default) state.
//
// For more details on configuring the GPIO peripheral functionality,
// please refer to the Personal Setup Peripheral Example/or the GPIO Setup Example.
void InitGpio(void)
{
EALLOW;

// Each GPIO pin can be:
// a) a GPIO input/output
// b) peripheral function 1
// c) peripheral function 2
// d) peripheral function 3
// By default, all GPIOs are input
GpioCtrlRegs.GPAMUX1.all = 0x0000; // GPIO function GPIO0-GPIO15
GpioCtrlRegs.GPAMUX2.all = 0x0000; // GPIO function GPIO16-GPIO31
GpioCtrlRegs.GPBMUX1.all = 0x0000; // GPIO function GPIO32-GPIO39
GpioCtrlRegs.GPBMUX2.all = 0x0000; // GPIO function GPIO48-GPIO63
GpioCtrlRegs.GPCMUX1.all = 0x0000; // GPIO function GPIO64-GPIO79
GpioCtrlRegs.GPCMUX2.all = 0x0000; // GPIO function GPIO80-GPIO95

GpioCtrlRegs.GPADIR.all = 0x0000; // GPIO0-GPIO31 are all input
GpioCtrlRegs.GPBDIR.all = 0x0000; // GPIO32-GPIO63 are all input
GpioCtrlRegs.GPCDIR.all = 0x0000; // GPI064-GPIO95 are all input

// Each input can have different restrictions
// a) Input signal sync to SYSCLKOUT
// b) Input proper sampling window
// c) Asynchronous input mode (only valid for peripheral inputs)
GpioCtrlRegs.GPAQSEL1.all = 0x0000; // GPIO0-GPIO15 sync to SYSCLKOUT
GpioCtrlRegs.GPAQSEL2.all = 0x0000; // GPIO16-GPIO31 sync to SYSCLKOUT
GpioCtrlRegs.GPBQSEL1.all = 0x0000; // GPIO32-GPIO39 sync to SYSCLKOUT
GpioCtrlRegs.GPBQSEL2.all = 0x0000; // GPIO48-GPIO63 sync to SYSCLKOUT

// Pull-ups can be disabled or enabled.
GpioCtrlRegs.GPAPUD.all = 0x0000; // Enable pull-ups GPIO0-GPIO31
GpioCtrlRegs.GPBPUD.all = 0xffff;//0x0000; // Enable pull-ups GPIO32-GPIO63
GpioCtrlRegs.GPCPUD.all = 0x0000; // Enable pull-ups GPIO64-GPIO79

//GpioCtrlRegs.GPAPUD.all = 0xFFFF; // Disable pull-up of GPIO0-GPIO31
//GpioCtrlRegs.GPBPUD.all = 0xFFFF; // Disable pull-up of GPIO32-GPIO34
//GpioCtrlRegs.GPCPUD.all = 0xFFFF // Disable pull-up of GPIO64-GPIO79

EDIS;

}

//==================================================================================
// End of file.
//=

...

#include "DSP2833x_Device.h" // DSP2833x Headerfile Include File
#include "DSP2833x_Examples.h" // DSP2833x Examples Include File

#define LED1 GpioDataRegs.GPADAT.bit.GPIO0 //Data register macro definition
#define LED2 GpioDataRegs.GPADAT.bit.GPIO1
#define LED3 GpioDataRegs.GPADAT.bit.GPIO2
#define LED4 GpioDataRegs.GPADAT.bit.GPIO3
#define LED5 GpioDataRegs.GPADAT.bit.GPIO4
#define LED6 GpioDataRegs.GPADAT.bit.GPIO5

interrupt void ISRTimer0(void);
void configtestled(void);

void main(void)
{
// Step 1. Initialize system control:
// PLL, WatchDog, enable peripheral clocks
// This function is in the DSP2833x_SysCtrl.c file.
InitSysCtrl();

// Step 2. Initialize GPIO:
// This function example in the DSP2833x_Gpio.c file
// explains how to set the default state of GPIO.
// InitGpio(); // Skip this function
InitXintf16Gpio(); //zq

// Step 3. Clear all interrupt vectors and initialize the vector table:
// Disable CPU interrupt
DINT;

// Initialize the default state of the PIE control register.
// The default state is that all interrupts and interrupt flags are cleared.
// This function is in the DSP2833x_PieCtrl.c file.
InitPieCtrl();

// Disable CPU interrupts and clear all CPU interrupt flags:
IER = 0x0000;
IFR = 0x0000;

// Initialize the address pointer of the interrupt vector table
// Interrupt service routine (ISR).
// Fill the table even if the interrupt is not used. This is for debugging.
// This function is in the DSP2833x_DefaultIsr.c file
// This function is in the DSP2833x_PieVect.c file
InitPieVectTable();
configtestled();

LED1=1;
DELAY_US(10);
LED2=1;
DELAY_US(10);
LED3=1;
DELAY_US(10);
LED4=0;
DELAY_US(10);
LED5=0;
DELAY_US(10);
LED6=0;
DELAY_US(10);

while(1){
LED1=~LED1;
DELAY_US(50000);
LED2=~LED2;
DELAY_US(50000);
LED3=~LED3;
DELAY_US(50000);
LED4=~LED4;
DELAY_US(50000);
LED5=~LED5;
DELAY_US(50000);
LED6=~LED6;
DELAY_US(50000);

}

}

void configtestled(void)
{
EALLOW;
GpioCtrlRegs.GPAMUX1.bit.GPIO0 = 0; // GPIO0 = GPIO0
GpioCtrlRegs.GPADIR.bit.GPIO0 = 1; // 输出
GpioCtrlRegs.GPAMUX1.bit.GPIO1 = 0; // GPIO1 = GPIO1
GpioCtrlRegs.GPADIR.bit.GPIO1 = 1; // 输出
GpioCtrlRegs.GPAMUX1.bit.GPIO2 = 0; // GPIO2 = GPIO2
GpioCtrlRegs.GPADIR.bit.GPIO2 = 1; // 输出
GpioCtrlRegs.GPAMUX1.bit.GPIO3 = 0; // GPIO3 = GPIO3
GpioCtrlRegs.GPADIR.bit.GPIO3 = 1; // 输出
GpioCtrlRegs.GPAMUX1.bit.GPIO4 = 0; // GPIO4 = GPIO4
GpioCtrlRegs.GPADIR.bit.GPIO4 = 1; // 输出
GpioCtrlRegs.GPAMUX1.bit.GPIO5 = 0; // GPIO5 = GPIO5
GpioCtrlRegs.GPADIR.bit.GPIO5 = 1; // 输出

EDIS;
}
//===========================================================================
// No more.
//===========================================================================