Realization of various wavelet transforms based on FPGA

灞波儿奔

Realization of various wavelet transforms based on FPGA [Copy link]

Based on the lifting framework wavelet transform method, various wavelet transforms can be realized by utilizing the programmable characteristics of FPGA. The lifting framework (LS) is a wavelet transform method proposed by Sweldens et al. in recent years. Its framework structure can effectively calculate DWT. For longer filters, the number of LS operations is nearly half of that of the filter bank operation method, which is more suitable for hardware implementation. Based on the framework structure of the lifting wavelet transform, the author uses the fully reconfigurable characteristics of FPGA to construct different wavelet transform kernels to meet the requirements of different application scenarios. In the structural design, a bottom-up design method is adopted. Each lifting step is represented by some programmable parameters to ensure that each step can be reconfigured. These parameters include the number of bits used to represent data and the channel depth of each internal mathematical module. In logic synthesis, different results can be obtained by changing the parameters according to the requirements of different wavelets. Taking the (5, 3) filter commonly used in image processing as an example, the wavelet transform kernel method of the filter based on the reconfiguration characteristics of FPGA is explained. The experimental results show that the lifting wavelet transform kernel designed using FPGA can meet the requirements of different occasions and different operations.
　　LS wavelet transform theory
　　The LS transform process is shown in Figure 1. The inverse transform is the same as the forward transform, but in reverse order. A time-discrete filter can be represented by its multinomial matrix, which is obtained by the Z transform of the odd-even sampling sequence of the impulse response. The essence of LS wavelet transform is to decompose the polynomial of the classical wavelet filter using the Euclidean algorithm.
　

　　Figure 1 Forward LS transform
　　A time-discrete filter H(z) is expressed as a polynomial as follows:

　　Based on FPGA, various wavelet transforms
　　He ( z ) and Ho ( z ) are realized respectively from

　　Implementing various wavelet transforms based on FPGA
　　The odd and even coefficients are obtained. The analysis filters H (z) and G (z) represent low pass and high pass respectively, and are expressed as a multi-phase matrix as

　　Based on FPGA, various wavelet transforms
　　P(z) can be simulated as analysis filters. According to the Euclidean algorithm, P(z) and P(z) can be decomposed into:

　　Implementation of multiple wavelet transforms based on FPGA
　　The above decomposition is not unique, there may be several pairs of {si (z)} and {ti (z)} filters, but all choices are equivalent for calculating DWT.
　　FPGA and implementation of lifting kernel
　　FPGA and reconfiguration characteristics
　　FPGA (Field Programmable Gate Array) is the result of the development of very large scale integrated circuit (VL, SI) technology and computer-aided design (CAD) technology. FPGA devices are highly integrated, small in size, and have the function of realizing special applications through user programming. FPGA generally consists of 3 programmable circuits and 1 SRAM for storing programming data. These 3 programmable circuits are: programmable logic block CLB (Configurable Logic Block), input/output module IOB (I/O Block) and interconnect resource IR (Interconnect Resource). As wavelet-based applications are becoming more and more widespread, it is of high application value and research value to use the flexible structure of FPGA to implement a reconfigurable lifting framework wavelet transform kernel. The design starts with basic mathematical modules and logic modules, using a bottom-up design approach. All library modules are described in VHDL language, allowing the size of the data channel of each unit to be selected according to the design accuracy requirements. In order to meet the needs of different environments, it is required to change the channel layer depth of a single module and consider compatibility with other devices. The lifting method is combined with the characteristics of FPGA, so that different lifting wavelet transforms can meet the needs of different applications on FPGA.
　

　　Figure 2 Lifting Kernel Structure
　　Implementation of Lifting Wavelet Transform Kernel
　　As shown in Figure 1, LS transform is a continuous and independent simple filtering operation process, which is the lifting step. The optimized lifting kernel structure can be derived from Figure 1. In recent years, the use of JPEG2000 standard for image transmission has become a hot topic, and many literatures have proposed different lifting wavelet transform structures.
　　However, most of these lifting structures only consider operability, while ignoring power consumption and flexibility. The lifting kernel structure proposed by the author (Figure 2) adopts a bottom-up design method different from the past. The main feature is that a separate pipeline multiplication unit and two addition units are specified. The multiplication unit is mainly used to deal with the symmetry problem of the filter coefficients, and the addition unit is used to implement analysis or synthesis transformation.
　　It is worth noting that all channel layers can be arranged with the designed library modules, so in order to ensure the synchronization of the internal IP core data flow, the front and back crossover problem must be considered. For example, at the addition output, a multiplier has been placed to allow the result of the lifting step to be normalized. This design method can achieve the highest data accuracy and the fastest running speed. In addition, the integer math unit is easier to perform deep pipeline operations and obtain high data throughput. The structure proposed in Figure 2 takes into account both operability and application flexibility. Since the running speed is improved, the power consumption is reduced.
　　Logic synthesis results
　　First, VHDL language is used to describe the transformation core structure designed by basic reconfigurable math modules and logic modules, and then functional simulation is performed in the MAX+PLUSⅡ integrated environment to realize the required transformation core, and finally FPGA logic synthesis is performed. The structure designed on Altera1's FLEX10K has obtained very satisfactory results after logic synthesis, as shown in Table 1. The results in Table 1 are directly obtained from logic synthesis, without considering the delay caused by various objective factors. More accurate timing analysis can be performed during the placement and operation process after the design process steps. In addition, in order to obtain complete analysis results, it is necessary to refer to the indicators provided by the FPGA manufacturer to estimate the power consumption. When using, programmable devices with low power consumption should be selected to better meet the requirements of different usage environments. Taking the (5, 3) filter as an example, the calculation of the (5, 3) wavelet requires the superposition of 4 lifting kernels. The proposed structure calculates the forward or inverse (5, 3) DWT, uses 15-bit sampling number and 12-bit synthesis filter coefficient for each frame of 1400×1400 pixels, runs at full clock frequency, performs 5-layer decomposition and reconstruction, and can process 25 frames of images per second with a power consumption of 267.6 mW. The
　
　　proposed reconfigurable lifting kernel structure adopts a special bottom-up design method to ensure maximum reusability and reconstruction characteristics. The simulation results show that the structure of the lifting wavelet transform kernel has achieved good results in terms of processing power and power consumption, especially in terms of processing speed, which can meet the real-time requirements of image processing. The further development in the future is to add more free parameters to the basic arithmetic module to ensure that the structure has better operability and reduce power consumption, which can meet the needs of different applications and has practical significance for reducing equipment costs and improving utilization efficiency.