FPGA controls TMS320C6678 power-on reset program

灞波儿奔

FPGA controls TMS320C6678 power-on reset program [Copy link]

module DSP_RST(
input clk_25m,
　input RESETSTAT, //DSP reset status 0 means reset status 1 means working status
input LOCKED, //Is the clock module normal?

output ref LRESETNMIENz = 1'b0,//局部复位管脚
output reg PORz=1'b0,//Power-on Reset
output reg RESETFULL=1'b0,//Full Reset
output reg RESET=1'b0
);

reg [2:0] RES_STATE=2'b00;
reg [15:0] por_counter=16'b0,resetfull_counter=16'b0,reset_counter=16'b0;

parameter IDLE=2'b00,PULL_RESET=2'b01,PULL_POR=2'b10,PULL_RESETFULL=2'b11;

always @(posedge clk_25m)
if(LOCKED==1)
begin
case(RES_STATE)
IDLE:
RES_STATE<=PULL_RESET ;
PULL_RESET: if(reset_counter<25000)
begin
reset_counter<=reset_counter+16'b1;
RES_STATE<=RES_STATE;
RESET<=1'b0;
PORz<=1'b0;
RESETFULL<=1'b0;
end
else
begin
RESET<=1'b1;
LRESETNMIENz<=1`b1;//禁止局部复位。
RES_STATE<=PULL_POR;
end
PULL_POR: if(por_counter<25000)
begin
por_counter<=por_counter+16'b1;
RES_STATE<=RES_STATE;
PORz<=1'b0;
end
else
begin
PORz<=1'b1;
RES_STATE<=PULL_RESETFULL;
end
PULL_RESETFULL:if(resetfull_counter<25000)
begin
resetfull_counter<=resetfull_counter+16'b1;
RES_STATE<=RES_STATE;
RESETFULL<=1'b0;
end
else
begin
RESETFULL<=1'b1;
RES_STATE<=RES_STATE;
end
endcase
end
else
begin
reset_counter<=16'b0;
resetfull_counter<=16'b0;
por_counter<=16'b0;
RES_STATE<=IDLE;
RESET<=1'b0;
PORz<=1'b0;
RESETFULL<=1'b0;
end

endmodule