TMS320C6678 device configuration pins and power-on timing

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TMS320C6678 device configuration pins and power-on timing [Copy link]

(1) LENDIAN: Determines the big and small endianness of the DSP.
(2) BOOTMODE[12:0]: Determines the self-starting mode of the DSP (see BootLoader for the C66x DSP User Guide for details).
(3) PCIESSMODE: Determines whether the PCIe subsystem is in EP, legacy EP or RC.
(4) PCIESSEN: Determines whether the PICe subsystem is enabled. The default is disabled.
(5) PACKSEL: Determines whether the input clock of the network coprocessor is the core clock or the PASSCLK clock.
DSP power-on timing The power
-on timing of the DSP is the timing of the power-on reset.
Device initialization is divided into two stages:
(1) All power supplies are stable. Different power supplies have power supply timings, as shown in the timing diagram below.
(2) RESET, POR, and RESERFULL are pulled high in sequence, of course, including the stabilization of the clock input.
Note:
(1) During the power supply stabilization period, POR must remain at a low level, so it is pulled low before reset.
(2) DDRCLK and REFCLK should be triggered before POR is pulled high.
(3) Once DVDD18 power is obtained, RESETSTAT is pulled low.
Before DVDD18 power is supplied, all LVCMOS inputs and bidirectional pins cannot be driven low or pulled high.
(4) After DVDD18 is valid, RESETSTAT can be pulled high at any time. Under POR controlled boot, RESET must be pulled high before POR is pulled high.
(5) After the power supply is stable, POR must continue to maintain a low level for at least 100us. At this point, the power supply stabilization phase is over.
(6) After the power supply stabilization phase, the device initialization requires 500 REFCLK clock cycles. The maximum clock cycle is 33.33nsec, so a delay of 16us before the rising edge of POR is necessary. The clock must be active during the entire 16us period.
(7) After POR stabilizes at a high level, RESETFULL must remain low for 24 REFCLK clock cycles.
(8) At the rising edge of RESETFULL, the device locks the level of the GPIO configuration pin and then performs configuration. The delay until the reset status bit RESETSTAT signal is pulled high is about 10,000 to 50,000 clock cycles.
(9) The GPIO configuration must be maintained for at least 12 REFCLK clock cycles (transitions) before the rising edge of RESETFULL.
(10) The GPIO configuration must be maintained for at least 12 REFCLK clock cycles (transitions) after the rising edge of RESETFULL.
In general:
After the power supply of each power supply is normal and the clock of the DSP is stable, drive RESET, POR, and RESETFULL to be pulled high in turn, lock the GPIO level of the DSP reset configuration at the rising edge of RESETFULL, and then pull RESETSTAT high, and the DSP power-on reset is completed.