Understanding of Hyperlink Interface in TMS320C6678
[Copy link]
1. Use of hyperlink
1.overview
1. High-speed, low-latency, low-pin communication interface between DSPs, which can simulate a variety of currently used peripheral interfaces.
2. Hyperlink includes digital signals and sideband control signals. Digital signals are based on serdes, and sideband signals are based on LVCMOS. The current hyperlink provides a point-to-point connection.
2.feeatures
1. There are only 26 pins, serdes is used for data transmission, and LVCMOS is used for control signals
2. All signals are driven and provided by one device, and all LVCMOS sideband signals use source synchronous clocks
3. Each channel is 12.5G, 1 or 4 channels are used for sending and receiving, and can support serdes full speed, half speed, quarter speed and one eighth lower speed. Serdes automatically detects and corrects polarity, automatically identifies channels and corrects.
4. Based on simple packet mapping memory transmission protocol, write request, write data, read request, read feedback data, interrupt request, support a variety of excellent transmission.
5. Point-to-point connection, request and feedback data are multiplexed through a physical pin? Support host/peripheral and point-to-point communication modes
6. The provided LVCMOS pins can be used for blanking and power management, support flow control of a single channel in a single direction, and support power management of a single lane in a single direction
7. Automatically adjust Lane width in power saving mode.
8. Serdes internal loopback for diagnostic and debug mode
9. No external pull-up or pull-down resistors are required
10.64 hardware and software interrupts.
11.8 Interrupt Pointer Addresses
12. Packages that do not support feedback writing
13.TX and RX must run at the same speed.
14. There are no external control word commands in this version.
15. The maximum supported remote register is 64 bytes. Sending more than that will cause bus conflict.
16. Exclusive transfer operations are not supported.
17.CBA constant mode is not supported for bursts larger than 256-byte aligned burst
3.功能框图
1. The data stream from the FIFO reaches the wire through the MAC and PLS
2. Each lane can work at 12.5G, and Hyperlink has its own effective encoding method to support the physical layer. Compared with the traditional 8b10b encoding method, Hyperlink removes the encoding overhead.
3. Sideband signals provide flow control and power management control information. The hardware controls itself and the software cannot configure intervention. As follows:
4. Architecture
1. Hyperlink requires a reference clock to serve the SerDes module, and you can choose 156.25Mhz, 250Mhz, or 312Mhz.
2. Pin description, serdes is for data transmission, LVCMOS is the sideband signal for control. I counted a total of 26 lines, 8*2 LVCMOS lines, and 10 serdes lines. The specific functions are as shown below:
3.TXPM and TXFL control the TXDATA of serdes; RXPM and RXFL control the RXDATA of serdes.
4. Of the four bits D3D2D1D0 for power management and flow control management, only the first two bits D0D1 are valid. D0=1 indicates support for Baud higher than 12.5G, and D0=0 indicates support for 12.5G and lower. D1=1 indicates support for 4 channels, and D0=0 indicates support for 4 channels.
5. Activate the channel:
To activate the channel, the transmitter sends a power-up event via TXPM to inform the receiver. The receiver receives the power-up event via RXPM and then enables reception. After the receiver has fully synchronized with the transmitter's training sequence, the receiver sends an event back to tell the sender that the channel can now be used for data transmission. The receiver then detects the transmission and switches from the training queue to data reception mode.
To support symbol alignment within the serdes, PLS needs to be enabled to inform the serdes that symbol alignment will occur. The sync word contains a comma so that the serdes can easily complete it. Each lane needs symbol alignment, and depending on the state of other lanes, phase correction may occur on all active lanes. This allows the development of one channel to four channels without being taken down during the alignment process.
Flow control is transparent to the user, the receiver of the hyperlink automatically manages the transmission flow of available resources and limits the flow of the TX end through the sideband signal.
6. Power Management:
Hyperlink determines the power state of the channel based on the lane power management register and rules the related receivers into the same power state through sideband signals.
During the restart phase, the serdes are in power down mode like all the channels. After exiting power down mode, the Hyperlink module sends a message to the remote device over the sideband bus to request its capabilities. When the response is received, the Hyperlink automatically enters an operational state. The serdes are only brought out of reset when the PWRMGT register is cleared or a transfer is pending. The hyperlink module automatically changes power modes based on the PWRMGT register and the outbound load. By default, the hyperlink leaves the transfer link idle until a transfer arrives from the slave port on VBUS. The hyperlink then enters single channel mode to service the transfer and the power up process for one channel is completed. The hyperlink dynamically manages its power modules based on the traffic load. When one channel cannot keep up with the data transfer, the hyperlink automatically enters four channel mode, and if the traffic is less than one channel, it automatically switches to single channel mode. If the traffic decreases further, the hyperlink automatically enters zero channel mode, shutting down the serdes transfer until a transfer arrives on the channel. Transmit and receive are independently controlled, and some applications only transfer in one direction.
The transmission of different modes is controlled by the lane power management register.
7. Serdes configuration and clock
This module controls the development rate of hyperlink and provides the interface between the transmission and reception of hyperlink and the pins of external devices. The end of the document provides examples of configuring serdes. The serdes registers are chip-level and not in the configuration register space of hyperlin. Before operating these registers, the Kick register must be operated to allow permission to operate the registers.
The serdes depends on the hyperlink serdes PLL and the RATESCALE of the send and receive, the rate scaling factor. Loop bandwidth? loop bandwidth.
The main purpose of hyperlink serdes is to generate a high-frequency output clock from a low-frequency reference clock (REFCLK). The PLL output frequency is determined by MPY, which is in HYPERLINK_SERDES_CFGPLL and is calculated as follows:
PLL_OUTPUT=REFCLK*MPY
The output range must be in the range of 1.5625GHz to 3.125GHz.
In order to eliminate the interference caused by jitter, LOOP_BANDWIDTH is introduced to set the formula as follows:
PLL_BANDWIDTH = REFCLK/BWSCALE
The relationship between BWSCALE, PLL_OUT and LOOP_BANDWIDTH is shown in the following table. 8~30MHZ is a special range and can be configured according to the following table:
RateBITS can set a frequency coefficient, such as 0.25.0.5, etc. The calculation formula of LINRATE is as follows:
LINERATE=REFCLK*MPY/RATESCALE, maximum is 12.5GHZ
There is a reference configuration table as follows:
8.SerDes receiving interface
There are four data channels, which can be found in the HYPERLINK_SERDES_CFGRX[3-0] system level register. The ENRX field gives the status of the receiver module. The hyperlink automatically enables the receiver module. The main function of the receiver module is to process the data and clock when the receive signal comes. The CDR register configures this function. The purpose of the clock data recovery algorithm is to simplify RXp and RXn so that data samples can be extracted in the middle of the data transmission. This is to determine whether the sample is idle or needs to be transmitted earlier or later.
The signal loss situation can be detected and the registers of the LOS domain can be configured.
9.SerDes transmission interface
The ENTX domain register corresponding to the receiving interface can give the status of the transmitting interface, and the module is automatically enabled.
The transmit interface enables the transmit channel and provides signal modulation options in signal transmission, paying attention to the SWING, TWPRE, and TWPST1 registers.
10.SesDes training process
Once the PLL is set, stable, and locked, the sideband signal and training steps begin.
When a non-zero MPY value is written to the HYPERLINK_SERDES_CFGPLL register, the PLL is locked and the transfer step is triggered. To ensure that the hyperlink coordination registers are properly set during the initial training step and to enable auto-negotiation, the following steps need to be followed:
1. Do a good job of resetting
2. Exit the reset state and run the application
3. Configure the hyperlink register and the transmit and receive configuration registers of the SerDes
4. Configure the MPY and PLL registers. If the configuration is valid, the PLL will lock and give the expected frequency output.
5. HYperlink will wait for the SerDes PLL to lock and start the Hyperlink sideband signal and transmission steps.
SDCS1 (sleep_cnt) controls the identified channel to enter the sleep or enable state. This allows the power supply to stabilize before the link is established. This register is a stable state before controlling the link and recovery state.
Sleep masked symbol count = sleep_cnt x 16 x Unit Interval
Disable masked symbol count = disable_cnt x 16 x Unit Interval
The recommended value for sleep_cnt and disable_cnt is the maximum value 0xff
11.Hyperlink Protocol
h provides three types of transfer events, read, write and interrupt.
1. Hyperlink write operation
On receiving a write transfer from the slave VBUSM port, the write command is written into the outbound Command FIFO, and the data is immediately read from the FIFO and encapsulated into a write request packet. The outbound address transfer logic overly outputs the control information into the address field, and the packet is encoded and serialized before being transmitted to the remote device. The remote device receives the packet, deserializes, and decodes the received data. The remote h-module stores the received write data packet into the inbound commandFIFO. The inbound address transfer logic activates the new mapping and activates other control information for the write transfer such as security and PRIVID. The h-module inside the remote device initiates a VBUSM maste write operation based on the new address and other control information. The written data is landed to the remote device, and each write is 256B. If the data is larger than this, it is depacketized and the above steps are repeated for each 256B packet. See the red arrow in the figure below.
2. Hyperlink read operation
The hyperlink receives a read request from the VBUSM slave port. The read request is stored in the outbound command FIFO. The read command is stored in the outbound command FIFO. The output address conversion logic identifies the address to be read and adds control information, which is then packaged into a read request packet. This packet is encoded, serialized and sent to the remote device. The remote device receives the read request packet through its own h interface. The packet is deserialized, decoded and written to the inbound command FIFO. The remote device reads the read request packet from the inbound command FIFO and initiates a read request based on the address and control information. (Previously packaged in by the end that sent the read request). The read request is sent from the masterVBUSM port of the h to the end point between the slave port. When the h module of the remote device receives the read return data, the data is written to the return datd FIFIO and then serialized. The remote device sends the read return data out through the h module interface, and the local h module interface receives the data. The transfer size is 256B. If a transfer is larger than this, it will be depacketized. The specific paths are shown in red and blue in the figure below.
3. Hyperlink formatting
Hyperlink is transmitted to the remote device through control words and data words. Each Hyperlink packet includes one or two control words and multiple data words. Control words and control word extensions are defined in section 0 and 0 related places. When the extend control bit is 1, the extended control field will be included. You don't need to pay too much attention to the specific protocol information.
A data packet always starts with a control word. There are four types of control words: write post, read, interrupt and read data return. They are as follows:
The specific table for each bit is in the protocol section of the datasheet and needs to be matched.
4. Address Translation
Hyperlink has independent internal address and external address conversion modules. The function of ingress is to overwrite the control information to the relevant address, and the function of egress is to remap the incoming address to the relevant memory area. Hyperlink supports up to 64 different memory mappings. The actual address of each memory area can be placed on any 64KB address boundary, which means it needs to be 64KB aligned? The size of each mapped memory can be sized of power of two, starting with 256B.
The maximum mapped area size is 256M. Some transmission characteristics have been embedded in the control word, such as priority, supervisor, usage mode, etc.
The conversion format is to first package the slave's target address and the private ID of the security bit together to form an overlay domain. The lower part of the target address is taken out to form a lower portion of the slave address. This part is combined with the overlay threshold group to become an output hyperlink address. At the receiving end. There is a controller with the input end rxsecsel, which is used to select the security bit, and rxsegsel is used to output the seg value, the value of the segment. This segment value is more important, and it is combined with the lower part of the incoming address to generate a header and packaged into a new output address. The third one is privIDsel. There are 16 IDs in total, from 0 to 15, and their functions are currently unknown.
The output channel determines how the address is pruned to impart high-level control information such as security and privID to the remote device.
The generation of Tx address is divided into three stages: taking address, adding privid, and adding security bit, both of which have 16 different values.
The Rx address part is more complicated. The h module has a PrivID table with 16 values. Each entry value can be configured with a 4-bit privID. The mapping relationship of the incoming data packet is determined based on this value of the packet.
The two registers of privID, one is the sequence register and the other is the data register, both are 32 bits, but only 4 bits are useful, and the rest are written with 0. When checking, write the index register first, and then read the value register.
The address remapping at the receiving end mainly relies on a segment and length table to determine the mapped address. OFFSET_MASK is a cheap mask used for address remapping. There are 16 in total, and the table has 64 entries. Each entry can be independently programmed to map a piece of address.
The address of the RX end is equivalent to: Segment Address + (Rx Address & OFFSET_MASK), where 31:16 of the segment address comes from the segment/length table of RXSEG_VAL. , 0:15 bits are all 0. The size of each segment can range from 512B to 256M and must be aligned to a 64KB boundary.
A packaging process for sending addresses, examples that come with the manual, address conversion.
This is the receiving process. You can refer to the examples provided in the manual.
A packet can be up to 256 bytes, but both reading and writing are split into 64 bytes.
5. Interruptions
64 interrupt events. HW_EVENT must be configured individually, as follows:
Write the interrupt control index register baseaddress+0x64, write in decimal
INTEN, enable bit
SIEN: Whether the software can trigger an interrupt
INTTYPE: Level trigger or pulse trigger, can only be set to 0, root clock is related
INTPOL: Polarity selection, high level trigger or low level trigger.
ISEC: If set to 1, only the secure host can trigger a software interrupt event.
DNID: Not used, write 0.
MPS: used to send interrupt data packets to remote devices, only 3LSBs are valid, and the high MSBs are all 0.
VECTOR: When INT2CFG is set to 1, HW_EVENT[x] indicates which interrupt needs to be suspended. If INT2CFG is set to 0, HW_EVENT[x] indicates that the interrupt pointed to starts sending packets to the remote device with MPS and vector fields. Vector is very important and can be used to indicate which remote register needs to be suspended, or as an index to obtain the interrupt address, according to the int2cfg setting of the remote device.
The method to get the value of the interrupt control register is: write the value to the register related to the interrupt control register, and then read it from the location 0x04. There are 0 to 63 interrupts in total, of which 0-31 are interrupts from the chip level, and 32-64 are interrupt signals from the waiting queue of the QM module. When IINTPOL is written as 0, the queue is not empty and an interrupt is triggered. When it is written as 1, an empty queue triggers an interrupt. Software interrupts write to the SW_INT register.
| 
提升卡
变色卡
千斤顶
京公网安备 11010802033920号
