Experience in Application Test of DSP External SRAM

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Experience in Application Test of DSP External SRAM [Copy link]

DSP hardware test description:

Platform description:

Figure 1-1 Code Composer Studio 6.0.0.00190 C/C++ development environment
The hardware platform is based on the TMS320F28335 chip, and the software platform is based on TI's Code Composer Studio 6.0.0.00190 C/C++ development environment, as shown in Figure 1-1.

Work progress description:
1. Completed the complete test of the DSP external SRAM hardware. By modifying TI's official .cmd file and library function calls,
the functions in FLASH can be copied to the external SRAM for operation, greatly improving the running speed of the DSP program. Detailed instructions are attached.
2. Completed the RS485 driver writing and application testing.
3. Used the official ADC_DMA and I2C routines to complete the ADC and EEPROM tests, and integrated the ADC_DMA routines.
4. The company already has the code for CAN communication and speed interruption, but it has not been sorted out.
5. The built-in watchdog module of DSP has been turned on.

1. Application description of external SRAM extended by DSP (tested)

Preface: DSP can work at a frequency of 150MHz. In order to give full play to its high-speed operation characteristics,
the FLASH program content is generally copied to the external high-speed SRAM for operation. TMS320F28335 has 34K X 16bit SRAM inside.
TI divides the internal SRAM into multiple blocks (see F28335.cmd).

Generally, the program runs in the built-in FLASH. The running speed of the program in FLASH is determined by the reading speed of FLASH.
If the FLASH acceleration technology is not used, it is generally necessary to set the waiting time. In order to make the program run at high speed,
at least one SRAM must be expanded to run the DSP algorithm or interrupt function at high speed.

1. External SRAM partition description

The hardware of this project has expanded 256K 16bit SRAM with a clock delay of 10ns.
The SRAM model is: IS61LV25616AL-10T.
The location address is: 0x0200000. The first 128K is used as program space, and the last 128K is used as data space.
The location address is the same as the internal SRAM address of ARM. The reference content of the DSP Chinese data manual is shown in the figure below (can be enlarged):


Figure 1-2 DSP typical 16-bit and 32-bit data bus connection diagram The

data bus of the IS61LV25616AL-10T chip is 16 bits. The subsequent STM32F429 board also uses this chip, but adds high and low bit selection lines,
so it can read high and low bytes, which is more flexible than DSP: DSP reads at least 2 bytes at a time, and ARM can read any byte it wants. In addition, ARM has internal FLASH acceleration, which
can run directly at 180MHz, and the peripherals are 90MHz, but the performance difference is relatively small compared to DSP.

The physical address of the external SRAM controlled by the GPIO37/XZCS7 pin of the DSP is shown in the figure below:

Figure 1-3 Physical address of the external SRAM controlled by the GPIO37/XZCS7 pin Allocated


in the F28335.CMD file, the details are as follows:

XINTF zone 7 - program space
ZONE7A: origin = 0x0200000, length = 0x020000

XINTF zone 7 - data space
ZONE7B: origin = 0x0220000, length = 0x020000

2. Instructions for using external DATA SRAM If

the internal SRAM is not enough, use the external DATA SRAM, the usage is as follows
#pragma DATA_SECTION(bufferB, "ZONE7DATA");
uint16_t bufferB[512];

Simulation test results:

Observe the data 0x22000 area, you can see that the bufferB area is set with the correct data by the program.

2. Instructions for using external CODE SRAM

External interrupt functions or general functions use the following declaration format
#pragma CODE_SECTION(cpu_timer0_isr,"xintffuncs");
#pragma CODE_SECTION(cpu_timer1_isr,"xintffuncs");

The compiler will allocate these specific functions in a fixed FLASH area
The starting address is XintffuncsLoadStart and
the ending address is XintffuncsLoadEnd.
After initializing XINTF Zone 7 in the main program, call the following function to
copy the specific function in this area to the running program space of the external SRAM (0x0200000-0x021FFFF)
MemCopy(&XintffuncsLoadStart, &XintffuncsLoadEnd, &XintffuncsRunStart);

Frequently run or called capture functions, timer functions or specific algorithms can only be truly utilized when they are run in high-speed SRAM
to truly exert the actual performance of TMS320C28335.

Simulation test results:
cpu_timer0_isr and cpu_timer1_isr are located in the 0x200000-0x21FFFF area
Breakpoints are set for these two interrupt functions, and the interrupt operation can be entered normally.
The actual simulation results of the timer 0 interrupt function are shown in the figure below:

Figure 1-4 Comparison analysis of the timer 0 interrupt function before and after loading into the external SRAM

The actual breakpoint simulation of the timer 1 interrupt function is as follows (it is a lossless compressed image and can be enlarged):

Figure 1-5 Analysis of the running address of the timer 1 interrupt code
It can be concluded that in the disassembly window, the entry address of the timer 1 interrupt is 0x2002a, and the GPIO50 pin is flipped within the 1ms timer 1 interrupt to generate a square wave.


Figure 1-6 Screenshot of the application test of the timer 1 interrupt

The picture is relatively small because it is a picture saved to the USB flash drive using a small oscilloscope. When saved in csv format using the oscilloscope, there are only 2500 data.
The waveform recorder records data for a long time. It can store more than 1 million points of data in just a dozen seconds. Of course, ordinary .xls or .xlsx files cannot store this data.

2. Communication configuration description (in progress)
1. RS485 communication configuration and application test code
The following is the network reference code. The actual configuration is more complicated, so it is not briefly described here.
// Remap the interrupt of PIE - Timer 0

• EALLOW; //Remove register protection
• PieVectTable.TXBINT = &SCI_TX_isr;
• PieVectTable.RXBINT = &SCI_RX_isr;
• EDIS; // Enable register protection
• // Enable receive interrupt
• PieCtrlRegs.PIEIER8.bit.INTx3 = 1;
• // Enable transmit interrupt
• // PieCtrlRegs.PIEIER9.bit.INTx4 = 1;
• IER |= 0x100;
• // Global interrupt enable and higher priority real-time debug events
• EINT; //Global interrupt enable INTM
• ERTM; // Enable real-time debug interrupt DBGM

Figure 1-6 shows the general process of SCIC serial port sending and receiving.

Figure 1-7 SCIC serial port sending and receiving process

// Use TMS320F28335's SCIC serial port FIFO to send data. As long as the data packet does not exceed 16,
// you can put all bytes into FIFO directly without waiting, which greatly saves CPU time overhead
// The specific implementation is as follows. As for the official routine, wait for the current byte to be sent before sending the next one.
// This wastes too much time. Basically no one uses it in actual products
if(Flag_CpuTimer0){
Flag_CpuTimer0 = 0; // 10ms timing period
GpioDataRegs.GPBSET.bit.GPIO50 = 1; // RS485 DE = 1 RS485 switches to sending state

for(i = 0; i < 10; ++i){
ScicRegs.SCITXBUF = bufferA ; // Put 10 data into FIFO, and then automatically transfer them to the shift register in sequence
}
asm(" nop");
asm(" nop");
asm(" nop");
asm(" nop");
asm(" nop");
asm(" nop");
}
// RS485 is in the sending state, and the SCIC shift register is empty
if((GpioDataRegs.GPBDAT.bit.GPIO50 == 1)&&(ScicRegs.SCICTL2.bit.TXEMPTY == 1)){
GpioDataRegs.GPBCLEAR.bit.GPIO50 = 1; // RS485 DE = 0 RS485 turns to the receiving state
}

2. CAN communication configuration
in progress


III. Data memory configuration description (I2C)
512K byte EEPROM is expanded, the official I2C routine (non-GPIO simulation timing) is opened, and it has been tested OK.

4. Integrated power chip test (GPIO)
is mainly a test of power devices, in progress

5. Watchdog configuration description (completed)

Generally, embedded systems need to enable external or internal watchdogs to prevent unexpected CPU hangs and crashes

6. TI official CMD file description (the actual application file is slightly modified based on the official one)

There are three CMD files provided by TI: 28335_RAM_lnk.cmd, F28335.cmd, DSP2833x_Headers_nonBIOS.cmd

When debugging the program, add the 28335_RAM_lnk.cmd file to the project, and the program is loaded into SRAM to run.
When the actual product is running, the program needs to be downloaded to FLASH and started from FLASH. At this time, it is necessary to
Add the F28335.cmd file to the project and shield the 28335_RAM_lnk.cmd file. 0, length = 0x001000 //

on-chip RAM block L0 PAGE 0 RAML1 : origin =

0x000400, length = 0x001000 // XINTF zone 0 PAGE 0 0 RAML0 : origin = 0x008000, length = 0x001000 // on-chip RAM block L0 PAGE 0 0 RAML1 : origin = 0x000400, length = 0x000400 // on-chip RAM block M1 PAGE 1 0 RAMM0 : origin = 0x000050, length = 0x0003B0 // on-chip RAM block M0 PAGE 1 0 RAMM1 : origin = 0x000400, length = 0x000400 // on-chip RAM block M1 PAGE 1 0 ZONE0 : origin = 0x004000, length = 0x001000 // XINTF zone 0 PAGE 0 0 RAML0 : origin = 0x008000, length = 0x001000 // on-chip RAM block L0 PAGE 0 0 0x009000, length = 0x001000 // on-chip RAM block L1 PAGE 0 RAML2 : origin = 0x00A000, length = 0x001000 // on-chip RAM block L2 PAGE 0 RAML3 : origin = 0x00B000, length = 0x001000 // on-chip RAM block L3 PAGE 0 RAML4 : origin = 0x 00C000, length = 0x001000 // on-chip RAM block L1 PAGE 1 RAML5 : origin = 0x00D000, length = 0x001000 // on-chip RAM block L1 PAGE 1 RAML6 : origin = 0x00E000, length = 0x001000 // on-chip RAM block L1 PAGE 1 RAML7 : origin = 0x00F000, length = 0x001000 // on-chip RAM block L1 PAGE 1 Allocate DMA-accessible RAM sections: DMARAML4 : > RAML4, PAGE = 1 DMARAML5 : > RAML5, PAGE = 1

















DMARAML6 : > RAML6, PAGE = 1
DMARAML7 : > RAML7, PAGE = 1

Allocate uninitalized data sections:
.stack : > RAMM1 PAGE = 1
.ebss : > RAML4 PAGE = 1
.esysmem : > RAMM1 PAGE = 1

The official TI file DSP2833x_Headers_nonBIOS.cmd maps the special function registers (PAGE 1) as follows

DEV_EMU : origin = 0x000880, length = 0x000180 // device emulation registers
FLASH_REGS : origin = 0x000A80, length = 0x000060 // FLASH registers
CSM : origin = 0x000AE0, length = 0x000010 // code security module registers
ADC_MIRROR : origin = 0x000B00, length = 0x000010 // ADC Results register mirror 8 // CPU Timer0
registers ( CPU Timer1 & Timer2 reserved TI use) CPU_TIMER2 : origin

= 0x000C10, length = 0x000008 // CPU Timer0 registers (CPU Timer1 & Timer2 reserved TI use) PIE_CTRL : origin = 0x000CE0, length = 0x000020 // PIE control registers PIE_VECT : origin = 0x000D00, length = 0x000100 // PIE Vector Table DMA : origin = 0x001000, length = 0x000200 // DMA registers MCBSPA : origin = 0x005000, length = 0x000040 // McBSP-A registers MCBSPB : origin = 0x005040, length = 0x000040 // McBSP -B registers ECANA : origin = 0x006000, length = 0x000040 // eCAN-A control and status registers ECANA_LAM : origin = 0x006040, length = 0x000040 // eCAN-A local acceptance masks ECANA_MOTS : origin = 0x006080, length = 0x000040 // eCAN-A message object time stamps ECANA_MOTO : origin = 0x0060C0, length = 0x000040 // eCAN-A object time-out registers ECANA_MBOX : origin = 0x006100, length = 0x000100 // eCAN-A mailboxes ECANB : origin = 0x006200, length = 0x000040 // eCAN-B control and status registers ECANB_LAM : origin = 0x006240, length = 0x000040 // eCAN-B local acceptance masks ECANB_MOTS : origin = 0x006280, length = 0x000040 // eCAN-B message object time stamps ECANB_MOTO : origin = 0x0062C0, length = 0x000040 // eCAN-B object time-out registers ECANB_MBOX : origin = 0x006300, length = 0x000100 // eCAN-B mailboxes EPWM1 : origin = 0x006800, length = 0x000022 // Enhanced PWM 1 registers EPWM2 : origin = 0x006840, length = 0x000022 // Enhanced PWM 2 registers EPWM3 : origin = 0x006880, length = 0x000022 // Enhanced PWM 3 registers EPWM4 : origin = 0x0068C0, length = 0x000022 // Enhanced PWM 4 registers EPWM5 : origin = 0x006900, length = 0x000022 // Enhanced PWM 5 registers EPWM6 : origin = 0x006940, length = 0x000022 // Enhanced PWM 6 registers






























ECAP1 : origin = 0x006A00, length = 0x000020 // Enhanced Capture 1 registers
ECAP2 : origin = 0x006A20, length = 0x000020 // Enhanced Capture 2 registers
ECAP3 : origin = 0x006A40, length = 0x000020 // Enhanced Capture 3 registers
ECAP4 : origin = 0x006A60 , length = 0x000020 // Enhanced Capture 4 registers
ECAP5 : origin = 0x006A80, length = 0x000020 // Enhanced Capture 5 registers
ECAP6 : origin = 0x006AA0, length = 0x000020 // Enhanced Capture 6 registers

EQEP1 : origin = 0x006B00, length = 0x000040 // Enhanced QEP 1 registers
EQEP2 : origin = 0x006B40, length = 0x000040 // Enhanced QEP 2 registers

GPIOCTRL : origin = 0x006F80, length = 0x000040 // GPIO control registers
GPIODAT : origin = 0x006FC0, length = 0x000020 // GPIO data registers
GPIOINT : origin = 0x006FE0, length = 0x000020 // GPIO interrupt/LPM registers

SYSTEM : origin = 0x007010, length = 0x000020 // System control registers
SPIA : origin = 0x007040, length = 0x000010 // SPI-A registers
SCIA : origin = 0x007050, length = 0x000010 // SCI
- A

registers

-B registers

SCIC : origin = 0x007770, length = 0x000010 // SCI-C registers

I2CA : origin = 0x007900, length = 0x000040 // I2C-A registers

CSM_PWL : origin = 0x33FFF8, length = 0x000008 // Part of FLASHA. CSM password locations

PARTID : origin = 0x380090, length = 0x000001 // Part ID register location