STM32F407 external SRAM configuration

The following SRAM program was tested on the STM32F407 development board of the Qing Dynasty

Development board PCB complete project link: http://www.cirmall.com/circuit/7 ... F%EF%BC%81#/details

Taobao link: https://item.taobao.com/item.htm?id=557618550100

bsp_SRAM.c file

#include "sram.h"  

#include "      usart.h "  
/// 
...​ ​  //For IS61LV25616/IS62WV25616, the address line range is A0~A17  //For IS61LV51216/IS62WV51216, the address line range is A0~A18 #define Bank1_SRAM3_ADDR ((u32)(0x68000000))  //Initialize external SRAM void FSMC_SRAM_Init(void) {  GPIO_InitTypeDef GPIO_InitStructure; FSMC_NORSRAMInitTypeDef FSMC_NORSRAMInitStructure;   FSMC_NORSRAMTimingInitTypeDef readWriteTiming;  RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOB|RCC_AHB1Periph_GPIOD|RCC_AHB1Periph_GPIOE|RCC_AHB1Periph_GPIOF|RCC_AHB1Periph_GPIOG, ENABLE); //Enable PD, PE, PF, PG clocksRCC_AHB3PeriphClockCmd     (RCC_AHB3Periph_FSMC,ENABLE); //Enable FSMC clockGPIO_InitStructure.GPIO_Pin   = GPIO_Pin_15; //PB15 push-pull output, control backlightGPIO_InitStructure.GPIO_Mode   = GPIO_Mode_OUT; //Normal output modeGPIO_InitStructure.GPIO_OType   = GPIO_OType_PP;//Push-pull output   GPIO_InitStructure.GPIO_Speed ​​= GPIO_Speed_50MHz;//100MHz   GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP;//Pu-up   GPIO_Init(GPIOB, &GPIO_InitStructure);//Initialize//PB15 push-pull output, control backlight GPIO_InitStructure.GPIO_Pin = (3<<0)|(3<<4)|(0XFF<<8);//PD0,1,4,5,8~15 AF OUT   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;//Multiplexed output   GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;//Push-pull output   GPIO_InitStructure.GPIO_Speed ​​= GPIO_Speed_100MHz;//100MHz   GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP;//Pu up   GPIO_Init(GPIOD, &GPIO_InitStructure);//Initialize     GPIO_InitStructure.GPIO_Pin = (3<<0)|(0X1FF<<7);//PE0,1,7~15,AF OUT   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;//Multiplexed output   GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;//Push-pull output   GPIO_InitStructure.GPIO_Speed ​​= GPIO_Speed_100MHz;//100MHz   GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP;//Pu up   GPIO_Init(GPIOE, &GPIO_InitStructure);//Initialize     GPIO_InitStructure.GPIO_Pin = (0X3F<<0)|(0XF<<12);//PF0~5,12~15   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;//Multiplexed output   GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;//Push-pull output   GPIO_InitStructure.GPIO_Speed ​​= GPIO_Speed_100MHz;//100MHz   GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP;//Pu up   GPIO_Init(GPIOF, &GPIO_InitStructure);//Initialize   GPIO_InitStructure.GPIO_Pin =(0X3F<<0)| GPIO_Pin_10;//PG0~5,10   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;//Multiplexed output   GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;//Push-pull output












    









   


































  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz;//100MHz
  GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP;//上拉
  GPIO_Init(GPIOG, &GPIO_InitStructure);//初始化 
 
 
  GPIO_PinAFConfig(GPIOD,GPIO_PinSource0,GPIO_AF_FSMC);//PD0,AF12
  GPIO_PinAFConfig(GPIOD,GPIO_PinSource1,GPIO_AF_FSMC);//PD1,AF12
  GPIO_PinAFConfig(GPIOD,GPIO_PinSource4,GPIO_AF_FSMC);
  GPIO_PinAFConfig(GPIOD,GPIO_PinSource5,GPIO_AF_FSMC); 
  GPIO_PinAFConfig(GPIOD,GPIO_PinSource8,GPIO_AF_FSMC); 
  GPIO_PinAFConfig(GPIOD,GPIO_PinSource9,GPIO_AF_FSMC);
  GPIO_PinAFConfig(GPIOD,GPIO_PinSource10,GPIO_AF_FSMC);
  GPIO_PinAFConfig(GPIOD,GPIO_PinSource11,GPIO_AF_FSMC);
GPIO_PinAFConfig(GPIOD,GPIO_PinSource12,GPIO_AF_FSMC);
  GPIO_PinAFConfig(GPIOD,GPIO_PinSource13,GPIO_AF_FSMC);
  GPIO_PinAFConfig(GPIOD,GPIO_PinSource14,GPIO_AF_FSMC);
  GPIO_PinAFConfig(GPIOD,GPIO_PinSource15,GPIO_AF_FSMC);//PD15,AF12
 
  GPIO_PinAFConfig(GPIOE,GPIO_PinSource0,GPIO_AF_FSMC);
  GPIO_PinAFConfig(GPIOE,GPIO_PinSource1,GPIO_AF_FSMC);
GPIO_PinAFConfig(GPIOE,GPIO_PinSource7,GPIO_AF_FSMC);//PE7,AF12
  GPIO_PinAFConfig(GPIOE,GPIO_PinSource8,GPIO_AF_FSMC);
  GPIO_PinAFConfig(GPIOE,GPIO_PinSource9,GPIO_AF_FSMC);
  GPIO_PinAFConfig(GPIOE,GPIO_PinSource10,GPIO_AF_FSMC);
  GPIO_PinAFConfig(GPIOE,GPIO_PinSource11,GPIO_AF_FSMC);
  GPIO_PinAFConfig(GPIOE,GPIO_PinSource12,GPIO_AF_FSMC);
  GPIO_PinAFConfig(GPIOE,GPIO_PinSource13,GPIO_AF_FSMC);
  GPIO_PinAFConfig(GPIOE,GPIO_PinSource14,GPIO_AF_FSMC);
  GPIO_PinAFConfig(GPIOE,GPIO_PinSource15,GPIO_AF_FSMC);//PE15,AF12
 
  GPIO_PinAFConfig(GPIOF,GPIO_PinSource0,GPIO_AF_FSMC);//PF0,AF12
  GPIO_PinAFConfig(GPIOF,GPIO_PinSource1,GPIO_AF_FSMC);//PF1,AF12
  GPIO_PinAFConfig(GPIOF,GPIO_PinSource2,GPIO_AF_FSMC);//PF2,AF12
  GPIO_PinAFConfig(GPIOF,GPIO_PinSource3,GPIO_AF_FSMC);//PF3,AF12
  GPIO_PinAFConfig(GPIOF,GPIO_PinSource4,GPIO_AF_FSMC);//PF4,AF12
  GPIO_PinAFConfig(GPIOF,GPIO_PinSource5,GPIO_AF_FSMC);//PF5,AF12
  GPIO_PinAFConfig(GPIOF,GPIO_PinSource12,GPIO_AF_FSMC);//PF12,AF12
  GPIO_PinAFConfig(GPIOF,GPIO_PinSource13,GPIO_AF_FSMC);//PF13,AF12
  GPIO_PinAFConfig(GPIOF,GPIO_PinSource14,GPIO_AF_FSMC);//PF14,AF12
  GPIO_PinAFConfig(GPIOF,GPIO_PinSource15,GPIO_AF_FSMC);//PF15,AF12

  GPIO_PinAFConfig(GPIOG,GPIO_PinSource0,GPIO_AF_FSMC);
  GPIO_PinAFConfig(GPIOG,GPIO_PinSource1,GPIO_AF_FSMC);
  GPIO_PinAFConfig(GPIOG,GPIO_PinSource2,GPIO_AF_FSMC);
  GPIO_PinAFConfig(GPIOG,GPIO_PinSource3,GPIO_AF_FSMC);
  GPIO_PinAFConfig(GPIOG,GPIO_PinSource4,GPIO_AF_FSMC);
  GPIO_PinAFConfig(GPIOG,GPIO_PinSource5,GPIO_AF_FSMC);
  GPIO_PinAFConfig(GPIOG,GPIO_PinSource10,GPIO_AF_FSMC);

   
  readWriteTiming.FSMC_AddressSetupTime = 0x02; //Address setup time (ADDSET) is 1 HCLK 1/36M=27ns readWriteTiming.FSMC_AddressHoldTime
  = 0x00; //Address hold time (ADDHLD) mode A is not used 
  readWriteTiming.FSMC_DataSetupTime = 0x08; ////Data hold time (DATAST) is 9 HCLK 6*9=54ns  
  readWriteTiming.FSMC_BusTurnAroundDuration = 0x00;
  readWriteTiming.FSMC_CLKDivision = 0x00;
  readWriteTiming.FSMC_DataLatency = 0x00;
  readWriteTiming.FSMC_AccessMode = FSMC_AccessMode_A; //Mode A 
    


 
  FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM3; // Here we use NE3, which corresponds to BTCR[4],[5].
  FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable; 
  FSMC_NORSRAMInitStructure.FSMC_MemoryType =FSMC_MemoryType_SRAM;// FSMC_MemoryType_SRAM; //SRAM   
  FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b;//Memory The data width is 16bit  
  FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode =FSMC_BurstAccessMode_Disable;// FSMC_BurstAccessMode_Disable; 
  FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low;
FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait=FSMC_AsynchronousWait_Disable;
  FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable; FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive   
  = FSMC_WaitSignalActive_BeforeWaitState;  
  FSMC_NORSRAMInitStructure.FSMC_ WriteOperation = FSMC_WriteOperation_Enable; //Memory write enable 
  FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable;  
  FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable; // Read and write use the same timing
  FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable;  
  FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &readWriteTiming;
  FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &readWriteTiming; //Read and write with the same timing


  FSMC_NORSRAMInit(&FSMC_NORSRAMInitStructure); //Initialize FSMC configuration


  FSMC_NORSRAMCmd(FSMC_Bank1_NORSRAM3, ENABLE); // Enable BANK1 area 3 

}
   

bsp_SRAM.h header file

#ifndef __SRAM_H #define
__SRAM_H    
#include "sys.h"  ///////////////////////////////////////////////////////////////////////////////////////////////////////////////////
void  FSMC_SRAM_Init( void ) ;  







 

#endif

SRAM test function

#define EXT_SRAM_ADDR   ((uint32_t)0x68000000)
#define EXT_SRAM_SIZE (1 * 1024 * 1024)

/*
*********************************************************************************************************
* Function name: bsp_TestExtSRAM
* Function description: Scan test external SRAM
* Parameter: None
* Return value: 0 means the test passed; greater than 0 indicates the number of error units.
*********************************************************************************************
*/
uint8_t bsp_TestExtSRAM(void)
{
uint32_t i;
uint32_t *pSRAM;
uint8_t *pBytes;
uint32_t err;
const uint8_t ByteBuf[4] = {0x55, 0xA5, 0x5A, 0xAA};


/* Write SRAM */
pSRAM = (uint32_t *)EXT_SRAM_ADDR;
for (i = 0; i < EXT_SRAM_SIZE / 4; i++)
{
*pSRAM++ = i;
}


/* Read SRAM */
err = 0;
pSRAM = (uint32_t *)EXT_SRAM_ADDR;
for (i = 0; i < EXT_SRAM_SIZE / 4; i++)
{
if (*pSRAM++ != i)
{
err++;
}
}


if (err > 0)
{
return (4 * err);
}


#if 0
/* Negate and write the data in SRAM*/
pSRAM = (uint32_t *)EXT_SRAM_ADDR;
for (i = 0; i < EXT_SRAM_SIZE / 4; i++)
{
*pSRAM = ~*pSRAM;
pSRAM++;
}


/* Compare the data in SRAM again*/
err = 0;
pSRAM = (uint32_t *)EXT_SRAM_ADDR;
for (i = 0; i < EXT_SRAM_SIZE / 4; i++)
{
if (*pSRAM++ != (~i))
{
err++;
}
}


if (err > 0)
{
return (4 * err);
}
#endif


/* The test is accessed in byte mode, the purpose is to verify the FSMC_NBL0 and FSMC_NBL1 lines*/
pBytes = (uint8_t *)EXT_SRAM_ADDR;
for (i = 0; i < sizeof(ByteBuf); i++)
{
*pBytes++ = ByteBuf[i];
}


/* Compare SRAM data*/
err = 0;
pBytes = (uint8_t *)EXT_SRAM_ADDR;
for (i = 0; i < sizeof(ByteBuf); i++)
{
if (*pBytes++ != ByteBuf[i])
{
err++;
}
}
if (err > 0)
{
return err;
}
return 0;
}

After multiple resets and multiple tests, the test is stable and passed

When you power on the GUI, just enter the address.