TI DSP C6000 structural knowledge

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TI DSP C6000 structural knowledge [Copy link]

(1) Harvard structure: Programs and data are stored in different memories, and each independent memory is independently addressed and accessed.

(2) Multi-stage pipeline: A DSP instruction (fetch, decode, fetch operands, execute). Each stage is called a pipeline.

(3) Hardware multiplier.

(4) Special DSP instructions.

(5) Multiple buses and multiple processing units.

TMS320C6000 series DSP
C67X includes: program fetch unit, instruction allocation unit, instruction decoding unit, (A/B) 2 groups of general registers (32 in total), 8 functional units, 1 group of control registers, control logic, test simulation and interrupt control logic. The structural block diagram of TMS320C67X DSP is shown in the figure below:

C674X has two levels of cache: 32Kb L1P program cache, 32Kb L1D data cache, and 256Kb L2 L2 cache. (Initially, the L2 cache is used as memory. L1 is used as cache).

On-chip peripherals: EMIFA/B, EDMA3 (x2), Timers, GPIO, UART (x3), SPI, I2C (x2), HPI, USB1.0/USB2.0, McASP (x2), EMAC bandwidth generator, VPIF, SATA, MMC/SD (8b) (x2), HPI, MDIO, 128KBRAM.