TI C6000 DSP Basics: GPIO

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TI C6000 DSP Basics: GPIO [Copy link]

1. DSP structure

(1) Harvard architecture: programs and data are stored in different memories, each of which is independently addressed and accessed.

(2) Multi-stage pipeline: a DSP instruction (fetch, decode, fetch operands, execute). Each stage is called a pipeline.

(3) Hardware multiplier.

(4) Special DSP instructions.

(5) Multiple buses and multiple processing units.

2. TMS320C6000 Series DSP

C67X includes: program fetch unit, instruction allocation unit, instruction decoding unit, (A/B) 2 groups of general registers (32 in total), 8 functional units, 1 group of control registers, control logic, test simulation and interrupt control logic. The structural block diagram of TMS320C67X DSP is shown in the figure below:

C674X has two levels of cache: 32Kb L1P program cache, 32Kb L1D data cache, and 256Kb L2 L2 cache. (Initially, the L2 cache is used as memory. L1 is used as cache).

On-chip peripherals: EMIFA/B, EDMA3 (x2), Timers, GPIO, UART (x3), SPI, I2C (x2), HPI, USB1.0/USB2.0, McASP (x2), EMAC bandwidth generator, VPIF, SATA, MMC/SD (8b) (x2), HPI, MDIO, 128KBRAM.

3. DSP Subsystem

4. General-Purpose-Input/Output(GPIO) Bank0-Band8 9*16=144 GPIOs

Once the GPIO Enable Register (GPIEN) is enabled, the GPIO pins can be used as general purpose inputs and outputs. The user can use the GPIO Direction Register (GPDIR) to independently configure each GPIO pin as input or output.

When configured as an output (GPxDIR bit = 1), the value of the GPIO Value (GPVAL) register: GPxVAL bit is sent to the corresponding GPn pin.

When configured as an input (GPxDIR bit = 0), the input status can be read from the corresponding GPxVAL.

In addition to the general purpose input/output functions, the edge detection logic of the GPIO peripheral reflects whether a signal change occurs on the specified GPIO pin configured as an input (GPxDIR bit = 0). The GPIO Delta Register reflects the change of the GPIO signal.

When the corresponding enable input changes from low to high, the GPxDH bit of GPDH is set to 1;

The GPxDL bit of GPDL is set to 1 when the corresponding enable input changes from high to low;

GPIO Enable Register (GPEN),

GPIO Direction Register (GPDIR),

GPIO Value Register (GPVAL),

GPIO Delta High Register (GPDH),

GPIO Delta Low Register (GPDL),

GPIO High Mask Register (GPHM),

GPIO Low Mask Register (GPLM),

GPIO Global Control Register (GPGC),

GPIO Interrupt Polarity Register (GPPOL)

//GPIO0[0] 1

// GPIO1[0] 17

// GPIO2[0] 33

// GPIO3[0] 49

// GPIO4[0] 65

//GPIO5[0] 81

// GPIO6[0] 97

// GPIO7[0] 113

// GPIO8[0] 129

宋元浩

Thanks for sharing