Samsung's next-generation 400+ layer V-NAND will be launched in 2026, and 0a DRAM will use VCT structure

On October 29, the Korea Economic Daily stated that according to the latest Samsung semiconductor memory roadmap it has, Samsung Electronics will launch the next-generation V-NAND with more than 400 stacked layers in 2026, while the 0a nm DRAM expected to be launched in 2027 will adopt the VCT structure.

Samsung's most advanced NAND and DRAM processes are currently the 9th generation V-NAND and 1b nm (12 nanometer-class) DRAM, respectively.

The report indicated that Samsung's 10th generation (i.e. next generation) V-NAND will be named BV (Bonding Vertical) NAND. This is because this generation of products will adjust the NAND structure from the current CoP peripheral upper unit to separately manufacturing the storage unit and peripheral circuit and then vertically bonding them. The overall idea is similar to Yangtze Memory's Xtacking and Kioxia-Western Digital CBA.

Korean media stated that this change can prevent damage to the peripheral circuit structure during the NAND stacking process, and can also achieve a bit density 60% higher than the CoP solution; the number of V11 NAND layers in 2027 will further increase, and the I/O rate can be increased by 50%; it is expected to achieve thousand-layer stacking in the future.

In the field of DRAM memory, Korean media said that Samsung Electronics will launch 1c nm DRAM in the first half of 2025, 1d nm DRAM in 2026, and the first generation of sub-10nm 0a nm DRAM memory by 2027, which is similar to what Lee Jeong-bae, head of Samsung's memory business, had previously shown.

The report believes that Samsung Electronics will introduce VCT (IT Home Note: Vertical Channel Transistor) technology at the 0a nm node to build a three-dimensional DRAM memory, further increasing capacity while reducing interference between adjacent cells. Earlier news indicated that Samsung will complete the development of a 4F2 VCT DRAM prototype next year.