Peng Qihuang: How does Siemens EDA support sustainable innovation and development of semiconductors?

On June 25-26, the 2021 Fifth Jiwei Semiconductor Summit with the theme of "The Heart and the Core are Imprinted, and the Changes are Kunpeng" was officially held in Haicang, Xiamen.

At the EDA/IP special forum on the 26th, Peng Qihuang, senior vice president of Siemens EDA and president of Asia Pacific, delivered a keynote speech on "How Siemens EDA supports the sustainable innovation and development of semiconductors."

Behind the progress of the semiconductor industry lies a golden rule: Moore's Law. Moore's Law was proposed by Gordon Moore, one of the founders of Intel. It states that the number of transistors that can be accommodated on an integrated circuit will double approximately every two years.

The often-cited "18 months" was proposed by Intel CEO David House: the expectation of 18 months to double the performance of a chip (that is, more transistors make it faster) is an observation of exponential growth.

The semiconductor industry has been developing roughly in accordance with Moore's Law for more than half a century, contributing to the world's economic growth in the second half of the 20th century and driving a series of technological innovations, social reforms, improvements in production efficiency and economic growth. Personal computers, the Internet, smartphones and other technological improvements and innovations are inseparable from the continuation of Moore's Law.

However, in recent years, there have been more and more voices about Moore's Law slowing down or failing. Will Moore's Law end? Peng Qihuang believes that the answer is yes. Even Gordon Moore, the inventor of Moore's Law, said that no exponential growth is sustainable. This is basic mathematical logic.

Peng Qihuang pointed out in his speech that although Moore's Law has been valid for decades, it should still be regarded as an observation of a phenomenon or a speculation about the future, rather than a physical law or a law of nature. From another perspective, there is no logical guarantee that the future growth rate will be the same as the past data, which means that there is no logical guarantee that Moore's Law will continue.

So, why has Moore's Law seemed to be basically useful for nearly 50 years? Peng Qihuang believes that "the learning curve and economies of scale are the real laws. The semiconductor industry combines these two, reducing costs through continuous innovation, and finding more industrial and life-improving applications to achieve greater economies of scale, which has created today's prosperity."

In this process, EDA has participated in the major ecosystem innovations in the semiconductor industry, including chip design, verification, manufacturing, packaging, testing, and system-level electronic design automation. The development of 5G/AI/Cloud/IoT has extremely high demands for large amounts of data and fast computing, which have put forward higher requirements for chip yield and advanced processes, and the EDA industry has also ushered in new opportunities and challenges. Peng Qihuang believes that there are three main challenges: rapid advancement of advanced processes, rapid improvement of product functions, verification, and digital twins.

Challenges in rapidly advancing advanced processes include: tool performance scaling, design for manufacturability, test and product yield, and computational lithography.

In this regard, Siemens provides Calibre and TESSENT tools. Among them, the Calibre toolset is based on advanced hierarchical algorithms and technologies, which can quickly, accurately and completely perform physical verification and parasitic extraction of mixed circuits. At present, it has been adopted by mainstream foundries around the world. The TESSENT product suite integrates multiple silicon testing and yield analysis solutions, covering areas such as automotive, logic, memory and mixed signal testing, and also involves silicon learning tools that can solve test startup, silicon characteristic characterization, diagnostic-driven yield analysis and fault analysis. Using the TESSENT tool helps to accelerate the design for testability (DFT) development and debugging cycle from design, verification to physical design.

Take Samsung's Galaxy mobile phone AP chip as an example. From S4 in 2013 to S20 in 2020, the chip size has grown from 137mm² to 92mm²; the number of transistors has grown from more than 1 billion to 8.5 billion. High-order nodes have greatly promoted the demand for EDA, and 7nm has grown to 35% of TSMC's revenue.

Challenges in rapidly improving product functionality include high-level synthesis (HLS), SSN flow scan test networks, power optimization, and 3D integration.

To this end, Siemens provides Catapult HLS and advanced heterogeneous packaging solutions, among which Catapult HLS greatly reduces the design work of custom accelerators. Through accurate implementation indicators and alternative architecture ratios, Tiny Yolo CNN reasoning speed is 10,000 times faster than software implementation, and each reasoning saves 12,000 times more effort than software implementation.

In the advanced heterogeneous packaging solution, Siemens provides heterogeneous planning and prototype design in the design phase; in the implementation phase, Siemens can provide physical implementation of silicon interposers and packaging; in the verification phase, Siemens provides 2.5/3D advanced logic and physical verification; in the analysis phase, Siemens provides thermal analysis and mechanical analysis for reliability.

Challenges in verification and digital twins include: hardware for application-scale performance, integrated simulation engines and co-modeling, analog mixed-signal, lifecycle management.

To meet this challenge, Siemens provides PAVE360, a closed-loop, cross-system integrated simulation verification solution that covers sensors, software, SoC chips, and electronic control units.

Finally, Peng Qihuang also mentioned how to maintain production growth and cost reduction through innovation in the "post-Moore's Law" era. He believes that 3D stacking technology has become a must-have application in memory and high-end chips such as HPC and mobile phone AP processors, and future innovations will inevitably rely on transistor materials such as optoelectronics and carbon nanotubes.

"We also expect that other high-tech innovative technologies such as quantum computing and human brain/DNA structures can continue to support the development of the semiconductor industry in the post-Moore's Law era," he said.