The first Chinese CPU instruction specification is released - LoongArch Infrastructure Manual

Publisher:sclibinLatest update time:2021-05-06 Source: 爱集微Keywords:CPU Reading articles on mobile phones Scan QR code
Read articles on your mobile phone anytime, anywhere

In mid-April, Loongson officially announced that the infrastructure of the Loongson autonomous instruction system architecture (Loongson Architecture, hereinafter referred to as Loongson Architecture or LoongArch) passed the evaluation of a well-known domestic third-party intellectual property evaluation agency and was officially released to the public at the main forum of the 2021 Information Technology Application Innovation Forum.

It is worth noting that unlike previous Intel/AMD's x86, Arm, RISC, MIPS, and SPARC instruction set specifications, LoongArch is the first CPU specification written in Chinese.

The Loongson architecture was launched by Loongson Technology based on 20 years of CPU research and ecological accumulation. It includes the infrastructure part and extended parts such as vector instructions, virtualization, binary translation, and nearly 2,000 instructions.


Complete independence, advanced technology and compatible ecology are the three main features of the Loongson architecture.

First of all, from the top-level planning of the entire architecture, to the functional definition of each part, and then to the details of the encoding, name, and meaning of each instruction, the architecture is independently redesigned, and the Loongson architecture has full autonomy.

Secondly, it discarded some outdated contents in the traditional instruction system that were not adapted to the current development trend of software and hardware design technology, and absorbed many advanced technological development achievements in the field of instruction system design in recent years. Compared with the original compatible instruction system, it is not only easier to design high-performance and low-power in hardware, but also easier to compile and optimize and develop operating systems and virtual machines in software.

Third, the design fully considers the compatibility ecosystem needs and integrates the main functional characteristics of various international mainstream instruction systems. At the same time, relying on the Loongson team's more than ten years of technical accumulation and innovation in binary translation, it can not only ensure the lossless migration of binary applications on existing Loongson computers, but also realize efficient binary translation of multiple international mainstream instruction systems.


Keywords:CPU Reference address:The first Chinese CPU instruction specification is released - LoongArch Infrastructure Manual

Previous article:Huawei P50 and P50 Pro have started mass production
Next article:Semiconductor employee salaries have reached a peak in recent years; RSA becomes a new measure to retain talent

Recommended ReadingLatest update time:2024-11-15 22:25

Study AVR (VI) CPU Status Register
The status register contains information about the result of the most recently performed arithmetic operation. This information can be used to implement conditional operations to change the program flow. Note that the status register is refreshed after all ALU operations are completed. In many cases, this will replace
[Microcontroller]
Principle and simulation study of transfer instructions applicable to RISC CPU
The RISC CPU processing method for transfer instructions introduced in this article is a 5-stage pipeline operation, namely instruction fetch, decoding, execution, memory access, and write back. The processing of transfer instructions is completed at the instruction fetch and decoding levels; the decoding level gives
[Power Management]
Principle and simulation study of transfer instructions applicable to RISC CPU
Intel plans to mass produce 5th generation CPU process within four years: equivalent to "1.8nm" level
In Stephen Chow's movie "Kung Fu", the Fire Cloud Evil God said a very classic sentence, "The martial arts in the world are invincible, only speed is indestructible." No matter how powerful the kung fu is, it will be defeated, but if the speed is extremely fast, no one can defeat you. This sentence is also applicable
[Semiconductor design/manufacturing]
Intel plans to mass produce 5th generation CPU process within four years: equivalent to
RISC-V, the third largest CPU architecture to replace x86 and ARM, is not qualified: at least not in terms of high performance.
Among the current main CPU instruction systems, x86 dominates the desktop and data center fields, ARM is the king of mobile chips, and the open and open source RISC-V has developed rapidly and has become the third largest CPU system. Since it is not subject to blockade restrictions, RISC-V has also been popular with
[Embedded]
The first Chinese CPU instruction specification is released - LoongArch Infrastructure Manual
In mid-April, Loongson officially announced that the infrastructure of the Loongson autonomous instruction system architecture (Loongson Architecture, hereinafter referred to as Loongson Architecture or LoongArch) passed the evaluation of a well-known domestic third-party intellectual property evaluation agency and wa
[Mobile phone portable]
Mixing and matching creates miracles: autonomous driving AI chips stage an architecture battle
After a wild growth period from 2016 to 2019 and a reshuffle in 2019, autonomous driving has entered a new stage of development. The technologies of industry-leading companies such as Google Waymo, Baidu Apollo, Tesla, Nvidia, and Mobileye are constantly iterating, and scenario-based applications are accelerating. For
[Automotive Electronics]
OK6410A Development Board (VIII) 67 linux-5.11 OK6410A Implementation of per-cpu linux kernel synchronization mechanism
What is the problem being solved? The race condition caused by SMP // Actually, it avoids the race condition of SMP, because each CPU has a variable with the same name, and there will be no race condition between SMPs Cannot solve race conditions caused by other reasons Other points It only makes sense under CONFIG_
[Microcontroller]
In four years, AI performance has increased 17 times! Intel Xeon 6 achieves outstanding results in the latest MLPerf test
The latest MLPerf benchmarks demonstrate the advantages of Intel Xeon processors in AI inference and general AI workloads. Latest release: Recently, MLCommons released the results of its industry-standard AI performance benchmark suite MLPerf Inference v4.1. Intel submitted six MLPerf benchmark
[Network Communication]
Latest Mobile phone portable Articles
Change More Related Popular Components

EEWorld
subscription
account

EEWorld
service
account

Automotive
development
circle

About Us Customer Service Contact Information Datasheet Sitemap LatestNews


Room 1530, 15th Floor, Building B, No.18 Zhongguancun Street, Haidian District, Beijing, Postal Code: 100190 China Telephone: 008610 8235 0740

Copyright © 2005-2024 EEWORLD.com.cn, Inc. All rights reserved 京ICP证060456号 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号