Big model of hot war between cloud and edge AI chips! Essential information on the first day of the 2023 Global AI Chip Summit

Similar to the idea of ​​​​integrating storage and calculation, every moment of thinking, hatched from the Intelligent Sensing Integrated Circuit and System Laboratory of Tsinghua University Electronics Department, connects the computing part to the sensor and directly uses analog data to perform operations, eliminating the ADC analog-to-digital conversion process. Significant power savings.

The intelligent sensing chip of Shengsi is based on the innovative near-sensing simulation computing architecture and can be implemented in various application scenarios such as intelligent driving and VR/AR. Take the car's Sentinel Mode application scenario as an example. This is a car mode that uses hardware to help car owners monitor vehicle safety when they are far away from the vehicle. The in-vehicle "sensory memory and computing integrated" co-processing chip can promote the sentry mode's consumption every night. The power consumption dropped from 5-8 degrees to 0.05 degrees; the standby power consumption dropped from the original 10W to 14mW, thus greatly improving the car experience.

▲Think deeply about CEO Zou Tianqi every moment

2. Data flow-driven reconfigurable computing: significantly improve chip utilization

The reconfigurable computing architecture configures hardware resources according to different applications or algorithms, allowing data to flow between computing units, reducing traditional decoding operations and memory access, which can greatly improve efficiency and save power consumption. In addition to Professor Wei Shaojun’s team, which has been developing this technology route for more than ten years, some AI chip companies have also begun to explore the commercial value of this technology route.

AMD's architectural innovation based on the XDNA AI engine is a data stream processing parallel computing array architecture used to provide high-speed, low-latency, and low-power real-time reasoning. Chiplets built based on the architecture of the XDNA AI engine build an on-chip heterogeneous computing platform with CPUs, FPGAs, etc., which can be extended to different platforms such as data centers, terminals (Ryzen AI), edge/embedded, etc. to meet diverse AI reasoning needs. .

The reconfigurable data flow architecture enables parallel data access and data calculation. Cai Quanxiong, co-founder and chief technology officer of Kunyun Technology, mentioned a formula: the measured performance of the chip = the theoretical peak computing power of the chip x chip utilization. Kunyun Technology's reconfigurable data flow architecture is to find breakthrough points from chip utilization, maximize the use of on-chip computing resources, and improve the measured performance of the chip. Compared with the instruction set architecture whose chip utilization rate is less than 35%, the CAISA chip based on Kunyun's reconfigurable data flow architecture can achieve a chip utilization rate of up to 95.4%.

▲Cai Quanxiong, co-founder and chief technology officer of Kunyun Technology

Cai Quanxiong said: "Kunyun does not pursue advanced processes, but innovates from the architectural side to provide the industry with the ultimate cost-effective AI computing power." Through the self-developed chip architecture CAISA 3.0 and the self-developed compiler RainBuilder, according to public test data, a 28nm Compared with a 16nm GPU chip, the CAISA chip with advanced technology can achieve up to 4.12 times the measured computing power. The chip has achieved mass production and large-scale implementation, providing AI video analysis solutions integrating computing power, algorithms, and platforms for more than 10 industries, and has successfully implemented more than 1,500 intelligent projects, covering smart security, smart energy, and industry. manufacturing and other fields.

Zhuhai Core Power specializes in the RPP (Reconfigurable Parallel Processor) architecture path that is both versatile and high-performance. Core Dynamics founder and CEO Li Yuan revealed that the RPP architecture arranges PE arrays in an assembly line manner. The measured area efficiency ratio can reach 7 to 10 times that of similar products, and the energy efficiency ratio is also more than 3 times. In other words, in the same calculation, It only takes up a smaller chip area under the pressure.

In addition, the RPP architecture is also fully compatible with CUDA, which means developers can directly use the CUDA programming language to write programs without complex code conversion. Currently, Core Power’s first GPGPU chip based on reconfigurable architecture, RPP-R8, has been successfully taped out and has achieved small-scale mass production.

▲Li Yuan, founder & CEO of Zhuhai Core Power

3. Reconstruct the computing architecture: innovation of software and hardware full-stack system architecture

Entering the new era of AI, Yin Wen of Xinzhi Technology believes that computing power innovation is no longer just an innovation in the microarchitecture and chip technology of a single processor, but requires a comprehensive innovation in the system architecture of the full stack of software and hardware. Future innovation opportunities come from the following aspects: Open universal instruction architecture, efficient fusion accelerator, heterogeneous interconnect bus and chip engineering, open source operator library, tool chain and software.

Based on this, Xinzhi Technology's architectural innovations around RISC-V open source instruction architecture, self-developed consistency bus, and WoW 3DIC can bring large-model AI inference chips that are 10 times more cost-effective. Looking to the longer-term future, Yin Wen believes that based on RISC-V open source instruction isomorphism and microarchitecture heterogeneity, open source software tool chain and independent consistency bus and chip engineering innovation, there will be opportunities to advance to the unified field of computing power in the future. The unified field of computing power will be more conducive to the formation of a larger new ecosystem of autonomous and controllable software, conform to the original characteristics of computing architecture, and help my country change lanes and overtake in the computing system.

▲Yin Wen, co-founder, chief chip architect and vice president of Xinzhi Technology

5. Forging elite weapons for AI chips, Chiplet assists large computing power chips to break through

As Moore's Law becomes increasingly difficult to maintain, how can we keep computing power growing even as we approach physical limits? Chiplet technology based on advanced packaging has become an effective way to balance economic benefits and improve chip performance in the post-Moore era.

The advantage of Chiplets is that they can achieve heterogeneous integration. This technical solution combines various chiplet modules using different processes and functions through advanced packaging technology, which can greatly improve the yield rate of large chips, reduce the cost of design and manufacturing links, and reduce the impact on advanced process production capacity. dependence. Classic AI chip products such as AMD MI300, Tesla D1, and Apple M1 Ultra all use advanced chiplet architecture.

Zhuhai GPGPU startup Core Power also fully recognizes the value of Chiplet technology in industrial development. It plans to connect Chiplets and I/O Dies to form a chip suitable for the edge, and use similar technology to connect multiple cores to provide higher computing power. . "

In February this year, Arctic Xiongxin released the first domestic intelligent processing chip "Qiming 930" based on heterogeneous chiplet integration. The chip is composed of 11 Chiplets spliced ​​together through a high-speed interface. It adopts 12nm process, 2.5D packaging, and domestically produced substrate materials. It can be used independently for AI accelerator cards, and can also be integrated through D2D expansion of multiple functional Side Dies.

Its founder, Ma Kaisheng, assistant professor at the Institute of Cross-Information at Tsinghua University, is often asked a question: Can two 2N process wafers be used through 3D integration to achieve the performance of the N process? The answer is yes, it is possible to use two 14nm chips to make a 7nm chip.

▲Ma Kaisheng, assistant professor of the Institute of Interdisciplinary Information at Tsinghua University and founder of Arctic Xiongxin

He listed 4 possible solutions: 1) Using a layer of wafers as a power supply network to solve the IR drop (power supply voltage drop) problem; 2) Multi-layer logic; 3) Mixing memory and logic; 4) Combining memory and logic , interconnection, storage, and power supply are coupled together.

Kuixin Technology, a Shanghai Internet IP product and Chiplet product supplier, focuses on high-speed interface IP and is committed to using Chiplets to crack the memory wall and I/O wall. Its vice president Wang Xiaoyang shared that considering that the use of HBM has limitations such as size and quantity, heat sensitivity, inflexible placement direction and adaptation, and process, Kuixin Technology is trying to decouple HBM HOST and SoC to create an M2link interconnection solution. Pull the distance between HBM and main SoC to 2.5cm. Using this solution, the available area of ​​SoC of the same size increases by 44%, the memory capacity bandwidth increases by 33%, and the maximum chip size is doubled.

▲Wang Xiaoyang, co-founder and vice president of Kuixin Technology

Conclusion: The cutting-edge confrontation between industry, academia, research and investment, and the Global AI Chip Summit heated up in Nanshan, Shenzhen

Since the first session in 2018, the Global AI Chip Summit has been held for five consecutive times, becoming one of the few industry summits in China that focuses on the field of AI chips and has great influence. In every session, you can hear the ideological exchanges between experts in the fields of industry, academia, research, application, and investment and financing of top AI chips. Diverse and exciting viewpoints collide here, sparking more sparks of inspiration for technology or product innovation.