A design of full-color large-screen display based on FPGA control

With the rapid development of digital technology, various digital display screens have emerged, including LED, LCD, DLP, etc. There are various control systems for various digital large screens, including ARM+FPGA offline control systems and PC+DVI interface decoding chip+FPGA chip online control systems. Here we will talk about a system that can not only be used to control the display of full-color LED large screens, but also can be used as a transmitter to output high-definition image data. The online control system used controls the full-color LED large screen. That is, the online control system of PC+DVI interface decoding chip+FPGA chip+output interface mode.

DVI Interface Overview

DVI stands for Digital Visual Interface, which is based on the TMDS (Transition Minimized Differential Signaling) electronic protocol as the basic electrical connection. TMDS is a differential signal mechanism that can encode pixel data and transmit it through a serial connection. The digital signal generated by the graphics card is encoded by the transmitter according to the TMDS protocol and sent to the receiver through the TMDS channel, and then decoded and sent to the digital display device.

There are currently two types of DVI interfaces. One is the DVI-D interface, which can only receive digital signals. The interface has only 3 rows and 8 columns with a total of 24 pins, one of which is empty in the upper right corner and is not compatible with analog signals.

The other is the DVI-I interface, which is compatible with both analog and digital signals. Fortunately, being compatible with analog signals does not mean that the D-Sub interface of analog signals can be connected to the DVI-I interface, but it must be used through a conversion connector. Generally, graphics cards that use this interface will come with related conversion connectors.

The interface used in this article is the DVI-D full data interface.

Principle of FPGA Controlled Full-Color LED Large Screen System

1 DVI decoding chip control principle

The input part of Figure 3 shows the control principle diagram of the FPGA chip controlling the decoding chip. The selected FPGA chip is the X3C1400A-5 of the Spantan_3 series of Xilinx. This chip can realize the control of the maximum clock of DDR_SDRAM to 200MHz. The DVI decoding chip used in this system is a decoding chip with the chip model tfp401 produced by TI. This chip receives the encoded image data transmitted by the computer DVI interface and outputs it to the DVI decoding chip. The chip decodes the serial data into 24-bit parallel data of the three primary colors R (Red), G (Green), and B (Blue), as well as line synchronization, field synchronization, data enable and clock signals, and then sends the decoded RGB image data, line synchronization, field synchronization, data enable and clock control signals to the FPGA chip, and buffers the image data into the FIFO of the FPGA chip. It should be noted here that when the resolution of the captured image is very large, the clock signal of the data transmission can reach up to 165MHz, and the output parallel image data is 24-bit data, so the maximum bandwidth can reach 3.96GHz. The bandwidth requirements must be considered when selecting external memory.

Figure 1 DVI-D interface

DDC: Display Data Channel (display data channel) ---- refers to the communication method between the host and the display device. Based on the end-user plug-and-play function requirements, VESA defines the DDC standard. Including DDC1/DDC2B/DDC2B+ and other methods. DDC2B is a quasi-bidirectional communication between the host and the display device, based on the I2C communication protocol. Only when the host sends a demand signal to the display and receives a response from the display, will the EDID data be sent. EDID: Extended Display Identification Data (external display device identification data) ---- refers to the display device data transmitted in DDC communication. EDID contains the basic parameters of the display device, such as manufacturer, product name, maximum line frequency, supported resolution, etc. The E2PROM in the figure is an important memory, which stores parameters such as manufacturer, product name, maximum line frequency, supported resolution, etc. transmitted by the computer. Only when the memory is working, the DVI interface can work normally. The data channel displayed by the memory is DDC. When it is plugged into the DVI interface here, there is a pull-up resistor for indication. The computer will automatically input various parameters into the memory, so that image data with various parameters as standards can be output from the DVI interface.

Figure 2 DVI-I interface

[page]

2 Select the buffer memory to store the image data

According to the bandwidth requirements for collecting image data mentioned above, DDR-SDRAM memory is used here, with a maximum clock of 200MHz and a data bit width of 16 bits. Therefore, the maximum bandwidth can reach 6.4GHz, and the utilization rate can reach 65% to meet the bandwidth requirements of the above-mentioned DVI interface chip input to the FPGA chip.

Since the maximum clock of the image data input from the DVI chip to the FPGA chip is 165MHz, which is not synchronized with the clock frequency of 200MHz output to the DDR-SDRAM memory, an asynchronous FIFO is used in the FPGA chip for buffering. The image data input from the DVI decoding chip is buffered into a FIFO with a width of 24 bits and a depth of 2048. The input clock is calculated based on the input image resolution, and the maximum output clock is 165MHz. The data is then output from the FIFO buffer period to the DDR-SDRAM memory, where the clock of the image data output to the DDR-SDRAM is 200MHz, and the output clock is always double data rate, that is, the data effective clock can reach 400MHz. The image data in the DDR-SDRAM memory is then output to the FPGA chip. In the buffer stage of outputting to the FPGA chip, the FIFO is needed to buffer the output to the external interface chip.

3 Image Processing

Since the brightness of the image seen by the human eye is nonlinear, the image output to the memory of the system is linear, so correction processing is required. Here, the gamma correction algorithm is used for processing. Y=KXr. The implementation process of gamma correction by the FPGA chip is to map the data, and map the image data output from the FIFO to the external interface one by one. The output image is obtained, and the corrected image data is output to the external device from the output interface.

Figure 3 Schematic diagram of FPGA-controlled full-color large-screen LED system

4 Two output interface modes for different fields

①The output of the FPGA chip is connected to the drive current chip

This interface is suitable for the output of multi-channel drive current chips. The FPGA chip output pin timing is used to control the multi-channel external drive current chips. The drive current chips then control the RGB light-emitting diodes, and finally display the image that the entire computer wants to display on the large-screen LED.

②The receiving end is an Ethernet cable interface

This interface is suitable for outputting images from a DVI decoding chip interface. This interface can be used to transmit image information over long distances and is applied to large-screen LED displays.

Advantages of using DVI interface for display devices

DVI transmits digital signals. Digital image information is directly transmitted to the display device without any conversion, which reduces the tedious conversion process from digital to analog and then to digital, greatly saving time. Therefore, it is faster and can effectively eliminate the phenomenon of smearing. When using DVI for data transmission, the signal does not decay, and the color is purer and more realistic. The computer transmits binary digital signals inside. When using the VGA interface to connect to the full-color LED large-screen display, the signal must first be converted into R, G, B three primary color signals and line and field synchronization signals through the D/A converter in the graphics card. These signals are transmitted to the full-color LED large screen through analog signal lines, and the corresponding A/D converter is required to convert the analog signal into a digital signal again before the image can be displayed on the full-color LED large screen. In the above-mentioned D/A, A/D conversion and signal transmission process, signal loss and interference are inevitable, resulting in image distortion or even display errors. The DVI interface does not need to perform these conversions, avoiding signal loss, and greatly improving the clarity and detail expression of the image.

Conclusion

The FPGA chip implemented in this design system controls the full-color large-screen image display system. It can not only be used for the display of full-color LED large-screen control systems with small size resolution (256×192), but also can transmit image data over long distances via Ethernet and send the image data to multiple receiving templates. The splicing of multiple receiving boards can be used to display large screens with high-definition color images with a resolution of (1920×1280).