WPG launches intelligent speech recognition solution based on Nuvoton Technology

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WPG launches intelligent speech recognition solution based on Nuvoton Technology

WPG Holdings announced that its subsidiary Pinjia has launched a voice recognition solution based on Nuvoton's ISD9160+Cyberon algorithm. This solution can support 20 local voice commands and can also use external SPI Flash to store sound data, realizing functions such as voice wake-up, voice recognition, voice playback, and MCU control.

Figure 1- Diagram of the speech recognition solution launched by WPG based on Nvuoton ISD9160 + Cyberon algorithm

Figure 1- Diagram of the speech recognition solution launched by WPG based on Nvuoton ISD9160 + Cyberon algorithm

Nuvoton's ISD9160 is based on the voice/audio system-on-chip (SoC) ChipCorder®, Cortex™-M0, and can provide a powerful and low-cost solution for applications that require voice/audio functions. Its highly integrated architecture 32-bit Cortex™-M0 processor, wide operating voltage range of 2.4 to 5.5V, I²S digital audio interface, 1W speaker driver, built-in flash memory, 3V regulator and multi-function GPIO are all designed to provide low-cost voice/audio system-on-chip for consumer products and industrial application markets.

Figure 2: System architecture of the speech recognition solution launched by WPG based on Nvuoton ISD9160 + Cyberon algorithm

Figure 2: System architecture of the speech recognition solution launched by WPG based on Nvuoton ISD9160 + Cyberon algorithm

Compared with ADPCM, the high compression algorithm of ISD9160 can achieve more than 50% compression, thus reducing memory size while delivering high-quality voice/audio. Its embedded flash memory can be used as user program code and audio storage space. ISD9160 can use external flash memory to store audio to extend playback time. Its highly integrated single-chip solution is very suitable for a wide range of voice/audio applications in industrial applications and consumer product markets.

Features

  • ARM ® Cortex™-M0 core, with a maximum execution speed of 50MHz

  • Deep power saving ( <1µA )

  • Sigma-Delta ADC with PGA and gain boost stage for microphone interface, 92dB signal-to-noise ratio ( SNR )

  • Audio PWM speaker driver, 1W at 5.5V

  • Analog GPIO ( Port B ) for sensor interfacing and capacitive sensing Programmable current source


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