Design of Synchronous Digital Multiplexer for Portable Satellite Station Based on FPGA

In portable digital satellite communication systems, in order to expand transmission capacity and improve transmission efficiency and meet the needs of transmitting several services at the same time, time division multiplexing is usually used to merge several low-speed digital code streams into a high-speed data code stream in a certain format so that it can be transmitted in one channel without interfering with each other. The equipment that realizes this function is a digital multiplexing system.

Portable satellite communications require high platform integration, high speed, low power consumption, small size and low cost. Field Programmable Gate Array (FPGA) is a structure composed of logic function blocks arranged in an array, and these function blocks are connected by programmable internal wiring to achieve certain logic functions. It is particularly suitable for product development and small-batch production with the above requirements.

In the circuit design stage, the FPGA development environment can perform various simulation analyses on the designed circuit in real time, improve the flexibility and reliability of the circuit design, and especially can directly carry out secondary development and function expansion on the finished product, which is flexible and portable. In the later stage, any logic signal can be simulated online in real time. This paper uses the Quartus II 5.1 software and VHDL hardware language to design and simulate, and realizes the design of a synchronous digital multiplexing system for a satellite portable station based on FPGA.

1 Design and Implementation

The synchronous digital multiplexer/demultiplexer completes the multiplexing and demultiplexing of the following services: 3 channels of audio data with a total of 48 kbps; 1 channel of 64 kbps synchronous data; 1 channel of 9.6 kbps asynchronous data; 1 channel of 128 kbps LAN data; 1 channel of 517.2 kbps video data. The design method adopts synchronous, fixed time slot allocation and bit-by-bit multiplexing.

1.1 Quasi-synchronous delay

Because the interface relationship between the digital multiplexer and the audio is the most complicated, the design focuses on the processing of the audio interface.

1.1.1 Ping-Pong Operation of Audio Interface

As shown in Figure 1, the dual-port RAM is used to complete the interface between the audio data and the multiplexer. The audio data interface is a DSP bus interface. In the first buffer cycle, the audio data is cached to the low-end address storage area of ​​the dual-port RAM, and the data multiplexing unit reads the audio data in the high-end address storage area of ​​the dual-port RAM; in the second buffer cycle, the audio data is cached to the high-end address storage area of ​​the dual-port RAM, and the data multiplexing unit reads the audio data in the low-end address storage area of ​​the dual-port RAM. This cycle repeats over and over again.

Figure 1 Ping-Pong operation diagram

In this way, the buffered data stream is sent to the multiplexer without any pause, which is a kind of pipeline processing. It completes seamless buffering and processing of data, saves buffer space, achieves the result of using low-speed modules to process high-speed data streams, and realizes parallel-to-serial conversion of data streams.

If the interface between audio data and multiplexer uses traditional caching method, it is easy to cause the audio data not to be written into the cache when the multiplexer reads the data, which can easily cause "clicking" sound. The ping-pong operation of the audio interface avoids this problem.

1.1.2 Provide lip synchronization mechanism

In digital satellite transmission systems, there is a unique audio and video synchronization problem, which is commonly known as lip sync. Since the signal processing time required for image compression coding is generally slower than the signal processing time required for sound compression coding, after the video and audio signals are decoded at the receiving end, it will be found that the audio is half a beat faster than the video. Usually, no sound can be heard when the mouth moves, or sound comes out when the mouth does not move, that is, the lip sync is not synchronized, giving the audience a poor subjective feeling. In order to avoid this problem, a lip sync unit is provided in the demultiplexer to delay the audio data program. By adjusting it, the audio and video synchronization at the receiving end can be guaranteed.

1.1.3 Solving the glitch problem in FPGA circuit design

In FPGA, when multiple signals change at the same time, some incorrect spike signals often appear. These spike signals are called "burrs". The occurrence of competition and adventure in combinational logic circuits will also cause "burrs". Its appearance will affect the stability and reliability of circuit operation, leading to erroneous operation and logical disorder of digital systems.

The design uses the D flip-flop's insensitivity to the glitches of the input signal to remove the glitches in the signal, but only the glitches that occur on the non-clock transition edge are removed significantly, and there is a certain delay. Therefore, the design tries to use synchronous timing circuits to implement the functions of each process module, and at the same time, the input and output data are sampled with a high clock to achieve the purpose of removing the glitches in the circuit.

1.2 Design

1.2.1 Frame structure

This unit does not require interconnection with other multiplexing and demultiplexing equipment, so a custom frame structure is used. The frame header uses a centralized frame code, and the frame header is fixed to 12 bits. The frame structure is shown in Table 1.

According to Table 1, we can calculate that when the frame length L of each frame is 7680 bits and the line rate R is 768 kbps, the frame period T is:

The frame rate F s is:

Table 1 Frame structure

1.2.2 Multiplexer

The multiplexer part is responsible for combining the information data of each branch and the frame header into one data stream. It consists of a clock sending circuit, a data receiving memory, a data buffer unit and a data multiplexing circuit. The clock sending circuit generates the time slot required for multiplexing the information data of each branch. The clock is obtained by using an internal clock source or by phase locking the receiving clock; the data receiving memory is a dual-port RAM used to receive digital audio data; the data buffer unit is used to adjust the phase of the synchronous data and other data to a phase that satisfies the multiplexing; the data multiplexing circuit combines the above data into one line data; the block diagram of the multiplexer is shown in Figure 2.

Figure 2 Multiplexer block diagram

1.2.3 Tap

The demultiplexer is responsible for decomposing a data stream into various branch information data. It includes data demultiplexing circuit, clock recovery circuit, data receiving memory and data buffer unit. The clock recovery circuit generates various clocks and corresponding branch time slots required for deframing. These clocks and the data received by the interface are sent to the data demultiplexing circuit together to search for frame synchronization words. When the synchronization rules are met, it is judged as synchronous. At the same time, the timing is forced to correspond to the data frame synchronization, and the branch information data is demultiplexed and sent to the corresponding decoding unit. If it is not synchronized, a synchronization/out-of-step alarm signal is given; the data receiving memory is a dual-port RAM used to send digital audio data; the data buffer unit is used to adjust the phase of the demultiplexed synchronization data to meet the phase of the data interface. The block diagram of the multiplexer is shown in Figure 3.

Figure 3 Block diagram of the splitter

1.2.4 Frame Sync Word Detection

For the centralized frame synchronization word mode, the frame synchronization word is a number of continuous code elements in the data stream, occupying adjacent time slots. Therefore, the frame code detection circuit is relatively simple and can be composed of a D flip-flop and an AND gate whose bit number is equal to the number of frame codes. The data is clocked into the D flip-flop bit by bit by the clock. Once the 12-bit frame code is shifted into the D flip-flop, that is, the 12 D flip-flops output the frame synchronization word, the AND gate outputs a pulse, otherwise the AND gate has no output. To prevent false synchronization, the device is considered synchronized only when the frame synchronization word is searched for 3 consecutive times, otherwise it is searched again. When the channel bit error rate is high, in order to avoid frequent device out of step, the device is considered out of step only when it loses step for 3 consecutive times.

The above method can prevent false locks and avoid starting unnecessary synchronous searches, making the device work more stable and reliable.

All the above functions, except interface conversion and clock phase lock, are implemented using FPGA devices and hardware design language. They are designed according to functional modularity, have good reusability, and can be easily transplanted.

1.2.5 Simulation and implementation

The multiplexer is developed on Altera's QuartusII5.1 hardware platform, written entirely in VHDL hardware description language, and undergoes timing simulation in the development environment of QuartusII5.1. The system simulation waveform is good, and except for signal delays within the allowable range, it can accurately realize the multiplexing and branching of digital signals. After being compiled and downloaded into programmable devices, the program has passed comprehensive experiments, achieved good results, and met the needs of the project.

2 System Synchronization Performance Analysis

During the transmission process, due to the influence of channel noise, errors will inevitably be introduced into the transmission code stream, resulting in the loss of system synchronization. Synchronization loss is a very serious problem that will lead to a serious decline in subjective quality and even make the entire system unable to work properly. Therefore, the synchronization performance of the multiplexing and demultiplexing system is a key link that affects the performance of the entire system.

At the transmitting end, the frame length of the data stream output by the multiplexing/demultiplexing system is L = 7 680 bits. At the beginning of each frame, there is a fixed value synchronization frame header with a code length of N = 12 bits. According to the literature [3], the average search time is:

In formula (3), P1 is the probability of false leakage on the synchronization word; Py is the probability of false alarm on the non-synchronization word; T is the data frame period. If the average bit error rate of the channel , the rate of the transmission stream is R = 768 kbit / s, then P1 = NP = 0. 001 2, Py = 2-12 = 0. 000 2, T = L / R, so Ta = 12. 68 ms.

If the influence of false alarm probability is not considered, the average confirmation frame loss time is:

In formula (4), β is the backward protection parameter, that is, the out-of-sync state is entered only after the synchronization word is lost for β consecutive times. Take β = 3, then Td = 25 ms. In addition, the average frame loss time is:

In formula (5), a is the forward protection parameter, that is, the synchronization state is entered after the synchronization word is found a times in succession. a = 3, then Tr = 50 ms. The average synchronization duration is:

So T1 = 1 607 h. From the above analysis, it can be seen that the multiplexing and demultiplexing system can confirm frame loss in a short time and quickly capture synchronization even without error protection; at the same time, it can maintain the synchronization state for a long time. Therefore, the multiplexing and demultiplexing system has good synchronization performance and can meet actual requirements under certain error protection measures.

3 Conclusion

All parts of the designed digital multiplexing system can be implemented on the FPGA chip using VHDL programming. The entire multiplexing and demultiplexing system functions can be integrated on a single chip, which not only saves hardware resources, reduces external wiring, simplifies the system, but also facilitates expansion, repeated programming and modification of programs. Multiplexing and demultiplexing with variable rates and variable frame structures can be achieved by simply modifying the corresponding control parameters in the FPGA and the external monitoring information. Experiments show that the system plays an important role in the FDMA portable satellite transmission platform and can improve the channel utilization and transmission capacity.