Driver design of micro printer based on FPGA and VHDL

Abstract: In order to replace the traditional use of single-chip microcomputer to drive the micro printer, the hardware control circuit of the printer is designed using the FPGA chip EP3C25Q240C8N of Altera Company, and the working timing of the micro printer is correctly controlled. The software uses the hardware description language VH DL to realize the timing control of the micro printer, and is downloaded to the FPGA through the Quartus software platform for debugging. It proves that this method is effective and can completely replace the traditional use of single-chip microcomputer to drive the micro printer. It has good anti-interference, high reliability and strong portability.

0 Introduction

FPGA stands for Field Programmable Array. It is a new type of high-performance programmable logic device developed on the basis of CPLD. FPGA has a high degree of integration, and its device density ranges from tens of thousands of gates to tens of millions of gates. It can complete extremely complex timing and combinational logic circuit functions, and is suitable for high-speed, high-density high-end digital logic circuit design. The new generation of FPGA even integrates the core of the central processing unit (CPU) or digital processor (DSP), and performs software and hardware co-design on a piece of FPGA, providing powerful hardware support for the realization of programmable system on chip (SOPC). For the drive of micro printers, the traditional method is to use a single-chip microcomputer to realize its timing control. With the popularization of FPGA in various fields and the need for micro printers, it is necessary to realize the timing control of micro printers by FPGA.

At present, various ASIC chip manufacturers have successively developed HDL languages ​​for their own purposes, but most of them are standardized and universal. The only one that is recognized is the VHDL language developed by the US Department of Defense, which has become the IEEE ST D_1076 standard. In addition, judging from the recent development of HDL languages, the hardware circuit design tools developed by many companies are gradually moving closer to the VHDL language, so that their hardware circuit design tools can also support the VHDL language.

VHDL language can support top-down and library-based design methods, and also supports FPGA design.

1 Introduction to Micro Printer

RD DH type micro printer adopts thermal heating dot matrix printing method. It is a small and fast printing output device. This type of printer can use standard parallel interface, RS 232 serial interface, TTL level serial port, 485 interface, USB interface, printing speed reaches 50 m/s, resolution is 8 dots/mm, 384 dots/line, and printing paper uses 57 mm thermal paper. It can print all Chinese characters and Western characters and icons in the first and second level Chinese character library of the national standard, a total of 8,178. The parallel interface of the micro printer is compatible with the CENTRONICS standard interface and can be directly controlled by the microcomputer parallel port or single-chip microcomputer. The pin number of its 26-wire double-row socket is shown in Figure 1. The signal definition of each pin of the 26 parallel ports is shown in Table 1.

Figure 1 Double-row socket pin number

Table 1 Pin definitions of micro printer 26 parallel port

The driving of the printer is mainly to correctly control its working timing. The timing diagram of the RD DH type parallel interface is shown in Figure 2.

Figure 2 Parallel interface timing diagram

2 Overall system design

The FPGA chip EP3C25Q240C8N of Altera's Cyclon? series is used to realize the hardware circuit control of the RD DH type micro printer, and the Quartus development tool is used to realize the software functions of the micro printer through VHDL language.

2.1 Hardware circuit design

Figure 3 shows the connection diagram between the printer and FPGA.

DATA 1~DATA8 represent the 8 data bits of the printer, their logic "1" represents high level, and logic "0" represents low level; STB is the data selection trigger pulse, and data is read in at the falling edge; ACK is the answer pulse, and the low level indicates that the data has been accepted; when BUSY is at a high level, it means that the printer is busy and no data is received at this time.

Since ACK and BUSY output a 5 V TTL level, and the FPGA I/O port standard is 3.3 V LVCMOS level, when these two signals are used as FPGA input signals, voltage division must be performed to ensure normal operation of the circuit.

Figure 3 Schematic diagram of FPGA and printer connection

2.2 Software Design

The software platform uses Altera's FPGA development platform Quartus.

Quartus provides a design environment that is independent of device structure. Designers do not need to be proficient in the internal structure of the device. They only need to use the input tools they are familiar with (such as schematic input or digital circuit description language input) to design. Quartus can be used to convert these designs into the format required by the final structure. Detailed knowledge about the structure has been written into the development tool software, and designers do not need to manually optimize their designs. The software development process is shown in Figure 4.

Figure 4 Software development flow chart

Use VHDL hardware description language for software design.

The driving of the micro printer is mainly to correctly control its working timing. The common state machine of VHDL is used to control the working timing of the printer. According to the timing shown in timing diagram 1, the state machine uses 4 states. The state transition diagram is shown in Figure 5.

In the initial state STATE0, the data enable trigger pulse signal STB is set to "1" (high level) to detect whether the printer is busy. If the printer is in the idle state (busy = "0"), it will enter the next state STATE1, otherwise (busy = "1"), continue to execute STATE0; in state STATE1, write data to the printer and directly enter the next state; in state STATE2, set the data enable trigger pulse signal STB to "0", the printer reads the data and enters the next state; in state STATE3, detect whether the data has been accepted. If the data has been accepted (ACK = "0"), the printer enters the initial state STATE0 and waits for new data. If the data has not been accepted (ACK = "1"), continue to execute STATE3 until the data is accepted.

Figure 5 State transition diagram

3 Conclusion

The micro printer driver designed using FPGA and V HDL hardware description language can complete the timing control of the printer through system debugging, and is currently in normal use in a certain type of tester. The design system has simple control, strong anti-interference, high reliability, good portability, and can be used in any system using FPGA chips, with certain application prospects.