Data Acquisition System Based on MAX7000 Series CPLD

CPLD is a complex PLD, specifically referring to those programmable logic devices with an integration scale of more than 1,000 gates. It consists of an AND array, an OR array, an input buffer circuit, and an output macro unit. It has outstanding features such as high gate circuit integration, configurable into multiple input and output forms, multi-clock drive, built-in ROM or FLASH (partially supports in-system programming), encryption, low voltage, low power consumption, and support for mixed programming technology. Moreover, the logic unit of CPLD is powerful, and general logic can be realized in the unit, so its interconnection relationship is simple, and the delay of the circuit is the delay of the unit itself and the lumped bus (usually in the range of several nanoseconds to tens of nanoseconds), and it can be predicted. Therefore, CPLD is more suitable for logic-type systems with complex logic, many input variables, but relatively few demands for triggers.

Introduction to MAX7000 Series CPLD and Its Development Platform

Due to the special requirements of the high-speed data acquisition system, among the many CPLD devices, ALTERA's MAX series devices were selected. The high performance and high density of the MAX series are based on its advanced MAX (Multiple Array Matrix) architecture, so it provides a very high cost-effectiveness for high-speed applications. The MAX7000 series also provides the industry's fastest programmable logic solution. It is based on CMOS EEPROM technology, with a minimum propagation delay of 3.5ns, can achieve counters with speeds higher than 200MHz, and provides a very wide range of choices for high-density devices, which is very suitable for high-speed design applications. The company's MAX+plusII software is an easy-to-use development tool with a friendly interface, high integration, compatibility with industrial standards, and support for FLEXMAXACEX 1K and other series products. And it provides a student version of the software for universities, which is similar to the commercial version in terms of function, but is only limited in the chips that can be used. Due to these advantages of the MAX7000 series, the following designs are all based on the MAX7000 series products.

Application of CPLD in High-Speed ​​Addressing

In general, data acquisition requires the CPU to read the results of A/D conversion and then transfer them to the off-chip memory, which requires at least 4 machine cycles. If a machine cycle is generally 1μs, the maximum sampling rate can only reach 250kHz, which is difficult to meet the needs of high-speed sampling. In this system, the sampled data is directly stored in the high-speed buffer RAM, and the memory addressing is completed by the address generator composed of ALTERA's EPM7032LC44-6. The write signal can use the clock signal of A/D conversion, but it needs to go through a series of frequency division and logical combination, or it can be generated by another circuit or placed in the address generator. The basic principle of EPM7032LC44-6 to form an address generator is to use 5 cascaded 74161s to form a 20-bit synchronous counter. The 20th bit is connected to the chip select line of the high-speed buffer RAM to switch the buffer memory group. Use CPU2's P1.7 to control the count enable terminal, and reset it asynchronously, so that the 20-bit address line output remains synchronized. Its specific implementation can use the graphic editing input or text editing input method. The VHDL language program is given below.

The simulation results are shown in Figure 2.

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CPLD constitutes data bus controller

In this high-speed data acquisition system, in order to increase the speed of data transmission and addressing, during normal sampling, the data bus and address bus do not need CPU control, and data storage is automatically completed by the system hardware. However, when CPU2 detects a sudden change in the input analog quantity, after a predetermined period of continuous sampling time, it will send control information to the address generator and data bus controller, stop storing sampled data and automatically generating addresses, and CPU2 will take control of the bus to operate on the data before and after the fault in the high-speed cache RAM. In order to avoid bus conflicts, a data bus controller is needed to handle the relationship between the system bus and the local bus.

EPM7064 can solve this problem very well. Inside EPM7064, a tri-state gate is used to isolate the read/write control lines of CPU2, 8 data buses, 12 data lines of AD9225 and an overflow line from the read/write control lines and data lines that control the high-speed buffer RAM. P1.7 of CPU2 is used as the control signal line of CPU2 or high-speed A/D control bus, so that the access control right of the buffer RAM data line can be easily switched. Considering the length of the article, the implementation program will not be given in detail. The implementation method of the address bus control logic is similar and will not be introduced again.

ISA bus interface composed of CPLD

In the PC series, the I/O space is independent, with a total of 1KB (address number 000H~3FFH). Since part of the I/O interface is distributed on the host motherboard and the other part is distributed on the expansion slot, the 1024 I/O port addresses are also divided into two parts, of which the first 512 are used by the interface controller on the motherboard and the last 512 are used by the interface control card in the expansion slot. And since part of the last 512 addresses have been configured as the interface of system resources, the I/O ports that can be truly designed and developed by users are few and discontinuous. In this way, the conventional method of using the address bus provided by the PC to address the dual-port RAM cannot be used, because this method can only address a few and discontinuous units. So this is a difficulty. For this reason, the method of using the data line of the PC to address the dual-port RAM is adopted, which only occupies three I/O ports to address the entire 4K RAM area.

The logic block diagram of the ISA bus interface circuit is shown in Figure 3.

The 8-bit data line, 10-bit address line, read/write control line IOW and IOR and power line in the ISA slot are used, and it is assumed that the three ports 390H, 391H and 392H are used. When the PC wants to access a certain address unit, it first sends the low 8-bit address to the data bus through the 390H port. At this time, the 390H signal and IOW signal sent by PC-AB output a latch pulse to the latch (L) through the decoding circuit, latching the low 8-bit address; then the high 4-bit address is sent to the data bus through the 391H port. At this time, the 391H signal and IOW signal sent by PC-AB output a latch pulse to the latch (H) through the decoding circuit, latching the high 4-bit address; finally, read and write are performed through the 392H port. As long as the 392H signal appears on the PC-AB, the decoding circuit outputs a low level to the /CS of the dual-port RAM, and then read and write operations can be performed according to the corresponding read/write control signals.

The VHDL file for implementing this interface using ALTERA's EPM7064SLC84-5 is as follows:

The simulation results show that this circuit design can fully realize the above functions. The simulation diagram when the PC uses port 392H to read the data in the dual-port RAM is shown in Figure 4.

CPLD is a new technology in the field of modern electronic engineering. It provides a circuit system design method based on computer and information technology, and improves the integration and reliability of the designed circuit. The author has tried to apply the MAX7000 series products launched by ALTERA to high-speed data acquisition. Specifically, the address generator, data bus controller and ISA bus interface are designed using EPM7032 and EPM7064. It has been applied in a precise fault location system of the power system.