Research and design of a stack space manager based on FPGA

The rapid development of aerospace, industrial control, automotive electronics and nuclear power plant construction has put higher and higher demands on the real-time performance of embedded operating systems. At the same time, due to the continuous improvement of the integration and speed of FPGA, the hardware implementation of embedded operating systems has become a development trend. Stack management in hard real-time operating systems plays a vital role in the real-time performance and reliability of the system. The traditional operating system kernel directly maximizes the stack space of each task, resulting in a large amount of storage space waste. In addition, the use of general RAM addressing cannot meet the rapid protection of the switched task information.

Based on the above problems, this paper proposes a stack space structure, designs a stack space manager with automatic verification function, and implements it on the Xilinx integrated development environment FPGA system.

1 Stack space structure

Stack space is a continuous memory space allocated according to the first-in-last-out (LIFO) principle, which can meet the needs of protecting task switching information and protecting processor status and task parameter data during interrupt response [1]. Each task is allocated a separate task stack and an interrupt nesting stack for responding to system interrupt tasks [2]. As shown in Figure 1, the stack space is divided into n task stacks and 1 interrupt nesting stack.

The task stack mainly protects the information of the switched task. The data it stores include: the first address of the task code, task parameters, local variables defined in the task, parameters and local variables of the called function, and the return address of each function in the task. The interrupt nesting stack stores the data of the interrupted task, including the context that needs to be saved when an interrupt occurs, the context that needs to be saved when interrupts are nested, and the local variables of the interrupt service program.

In a hard real-time operating system, when an interrupt or interrupt nesting occurs, the stack address pointer switches from the task stack to the interrupt nesting stack. When all interrupt service programs are executed, the stack address pointer switches from the interrupt nesting stack to the task stack and continues to execute the interrupted task. Compared with the previous operating system that uses the method of saving the data of the interrupted task to the corresponding task stack, this management method saves more stack space overhead [3, 4]. [page]

2 Overall structure of the stack space manager

In order to save RAM overhead, a stack space manager with LIFO and self-checking functions is constructed from the overall structure. The stack space manager structure includes a dual-port storage unit, a state control logic module, an address generation logic module, and an interrupt judgment logic. The state control logic module consists of three parts: empty/full flag generation logic, binary operation logic and flag register group; the address generation logic module consists of three parts: read/write address logic, interrupt stack logic and address register group.

As shown in Figure 2, the working process of the state control logic module is as follows: read the usage fcount signal value of the current task stack from the flag register group, and transmit the fcount signal value to the binary operation logic. When the read/write control signal is valid, the binary operation logic is valid, and the fcount signal value is modified. The modified value is used as the output value of USED and written back to the corresponding fcount bit of the flag register. The modified signal value is also used as the input signal of the empty/full flag generation logic. The empty/full flag generation logic generates a Full/Empty flag and writes the flag bit back to the corresponding Full/Empty bit of the flag register. The structure of the flag register freg is shown in Figure 3, and the initial value is 0000001000000000B.

The interrupt judgment logic is determined by the input signal INT and the flag register bit IntNesting value to determine whether it is valid. If an interrupt occurs, the interrupt stack logic is valid and the interrupt stack logic generates a read/write address. Otherwise, the read/write address logic is valid and generates the corresponding read/write address.

When the read/write control signal is valid, the address of the current task is read from the stack address register group, and the stack address pointer is generated through the read/write address logic or the interrupt stack logic as the push/pop address of the HOS stack space. When executing push, when the synchronous clock and the push control signal are valid, the interrupt judgment logic determines whether there is an interrupt or interrupt nesting. If not, the write address logic generates the push address; otherwise, the interrupt stack logic generates the write address. Similarly, when executing pop, when the synchronous clock and the pop control signal are valid, the interrupt judgment logic determines whether there is an interrupt or interrupt nesting. If not, the read address logic generates the pop address; otherwise, the interrupt stack logic generates the pop address. [page]

3 Stack space manager design

In order to quickly and effectively protect the information of the switched tasks and meet the requirements of the automatic inspection function, two logic modules are designed in the stack space manager design, namely the state control logic module and the address generation logic module. The state control logic module mainly generates the push/pop control signal and the Used signal, and the address generation logic module mainly generates the valid push/pop address. Based on the description of the overall structure and working process of the stack space manager, a simulation stack space manager is designed on the XUP Virtex II Pro series chip designed by Xilinx to simulate the management of 8 tasks. The depth of the task stack is 64 and the width is 16 bits. The depth of the interrupt nesting stack is 128 and the width is 16 bits. The capacity of the stack space is 10KB. In the design manager, the manager is ensured to be quickly synthesized and occupy as few FPGA resources as possible. The selection of storage units is the key. The system uses an 18KB BlockRAM resource on the FPGA and uses the IP core of the dual-port RAM storage module provided by ISE8.2i. If other methods are chosen, such as using triggers and registers to build storage units, the synthesis time is long and a large number of FPGA slice resources are occupied.

In actual embedded system applications, the depth and width of the stack space can be calculated according to system requirements, and the specific depth and width can be modified in the VHDL code.

3.1 Design of state control logic module

Since the empty/full status flag of the status flag register determines the stack space push/pop operation, how to design the empty/full status flag is the key. In order to ensure that the protected data can be correctly pushed and popped, and to prevent the memory from overflowing or overflowing, it is ensured that in the full state, the push operation cannot be performed; in the empty state, the pop operation cannot be performed. The generation process of the control signal is shown in Figure 4.

When designing the state control logic module, the prio_int signal drives four multiplexers to select each segment in the corresponding state flag register group, which has full signal value, empty signal value, fcount signal value and intNesting signal value. The empty/full signal and push/pop signal are used as combinational logic input signals to generate corresponding push_en/pop_en valid control signals, which determine whether the stack space performs push/pop operations.

When the push_en/pop_en control signal is valid, the binary operation logic is driven to add/subtract 1 and the operation result is output. The output signal value has three uses: (1) as the input signal of the empty/full flag state generation logic, which generates empty/full signals; (2) written back to the fcount bit corresponding to fregx; (3) as the Used output signal value, indicating the usage of the current task stack or interrupt nesting stack.

When designing the logic module for generating empty and full signals, the method of performing combinational logic judgment on each bit of the input signal is adopted, so that the signal is divided into two paths, one of which is used as the input signal of the AND gate combinational logic to generate the full signal. If each bit of the input signal is 1, the full signal is set to 1, otherwise it is set to 0; the other input signal as the non-combinatorial logic of the OR gate generates an empty signal. If each bit of the input signal is 0, the empty signal is set to 1, otherwise it is set to 0. In the entire logic module design, the combinational logic design is adopted to shorten the working delay and increase the system working frequency. [page]

3.2 Address generation logic module design

The stack address pointer SP determines the correct stacking and popping of the data in the stack space unit. The stack address pointer SP is obtained by how to drive the read/write logic module and the interrupt stack module. In order to ensure the validity and real-time performance of the protected data and prevent uncertain states, the data must be operated under the state of timing synchronization, as shown in Figure 5.

When designing the address generation logic, the stack address register group is first assigned an initial value. The simulation system manages 8 tasks and has 9 stack address registers, including 8 task stack address registers and 1 interrupt nested stack stack address register.

When the task priority Prio signal and the interrupt enable int_en signal drive the multiplexer at the same time, the stack address pointer SP selects the address of the current task stored in Pregx from the stack address register group. In the designed stack space manager, SP points to the address of the next storage unit in the stack space. If the push control signal is valid, SP is used as the addressing address of the stack space, data is written, and SP increases by 1; if the pop control signal is valid, SP decreases by 1, and the changed SP value is used as the addressing address of the stack space, and data is read out. After the operation is completed, the changed SP value is written back to the corresponding stack address register group Pregx.

4 Simulation result analysis

The capacity of this stack space manager is 10KB and the width is 16bit. Synthesis and simulation were performed in ISE8.2i development software. 294 Slices, 396 Flip-flop, 274 InputLUTs, 60 BoundedIOBs, and 1 BlockBRAMs were used in the design.

During simulation, decimal data was input. Figure 6 is the system timing simulation waveform.

(1) When INT is invalid, there is no interrupt or interrupt nesting in the system. When push is valid, the prio signal value is set to 2, and the data_in signal value is 32768 and 57908 respectively. During simulation, the output results are: the used signal values ​​are 1 and 2 respectively, and the ostcbstkptr signal values ​​are 128 and 129 respectively; similarly, when pop is valid, the prio signal value is set to 2, and the simulation results are observed: the dot_out signal values ​​are 32768 and 57908 respectively, the used signal values ​​are 1 and 0 respectively, and the ostcbstkptr signal values ​​are 129 and 128 respectively. It can be concluded that under the condition of no interrupt processing, according to the task priority prio, data is written and read in the task stack according to the LIFO principle, and each valid operation simultaneously modifies the used and ostcbstkptr signal values ​​of the current task.

(2) When INT is valid, an interrupt occurs in the system or there is interrupt nesting. When push is valid, set the prio signal value to 6 and the data_in signal value to 8192. The simulation results are: the used signal values ​​are 1, 2, 3, 4, and the ostcbstkptr signal values ​​are 576, 577, 578, and 579, respectively. Similarly, when pop is valid, set prio to 6. The simulation results at this time are: the data_out signal value is 8192, the used signal values ​​are 4, 3, 2, and 1, and the ostcbstkptr signal values ​​are 579, 578, 577, and 576, respectively. It can be seen that when an interrupt occurs or there is interrupt nesting in the system, data is written and read out in the interrupt nesting stack according to the LIFO principle, and each valid operation simultaneously modifies the used and ostcbstkptr values ​​of the interrupt nesting stack. [page]

From the above results analysis, it can be seen that the experiment verifies the correctness of the stack space manager and meets the requirements of system design.

This paper analyzes the stack space structure and the protection of the corresponding data information of the switched task, and divides the stack space into a reasonable structure. The experimental data show the feasibility and stability of the system. The stack space manager can effectively save the time of hard real-time operating system to allocate stack space and reduce RAM storage space. From the hardware point of view, it simplifies the design, reduces the cost and has certain use value. Currently, it is only simulated on the experimental platform. The next step is to apply the IP core of the stack space manager to the hard real-time operating system to improve the operating efficiency of the operating system.

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