Development of an electric bicycle charging system based on SPCE061A and CPLD

super_star

Development of an electric bicycle charging system based on SPCE061A and CPLD [Copy link]

Electric vehicles are favored by many users due to their features of no exhaust pollution, no noise, light weight and beautiful appearance. However, their use also reveals their limitations, that is, the capacity of the battery determines its scope of use, and there is a disadvantage of long charging time. At present, with the development of electric bicycles, the problem that needs to be solved urgently is how to achieve fast and flexible charging.

　　With the rapid development of electronic technology, programmable logic devices (FPGA, CPLD), and EDA technology, the top-to-down design method based on hardware programming language has brought revolutionary changes to the development and design of digital systems. The traditional method of using only single-chip microcomputers to achieve system control is being replaced by more and more latest design concepts with MCU+FPGA/CPLD as the core. The biggest advantage of adopting this hybrid design scheme is that the advantages of the two are complementary and the circuit structure is simple, which brings great convenience to the design of digital circuit systems. It is easy to modify the circuit online by using the flexibility of CPLD control to realize various complex digital logic controls, which greatly expands the functions of single-chip microcomputers. Moreover, due to the flexibility of hardware programming language and the in-system programming (In-SystemProgram) characteristics of CPLD, the system development cycle is greatly shortened. Based on the above ideas, an electric bicycle charging system based on SPCE061A and CPLD was developed.

　　1 System Hardware Design

　　1.1 System composition and functions

　　The charging system is composed of Lingyang SPCE061A single-chip microcomputer, charger, button, CPLD, ACM12864 LCD, host computer, voice circuit, etc. The charger uses a three-stage charging method of constant current, constant voltage and floating charge to charge the battery. The SPCE061A single-chip microcomputer controls six chargers to charge six batteries at the same time, and detects the three charging states of constant current, constant voltage and floating charge of each charger at the same time, and displays the working state of each charger through the ACM12864 LCD. The operation and stop of each charger can be selected by buttons, and the fast charging working mode or the normal charging working mode can be selected according to different needs to charge the battery. After the system is powered on and enters the working state, when the single-chip microcomputer detects the signal that the battery is full or the signal generated by other emergency situations, the charger can be automatically turned off to realize the intelligent operation of the charger. The voice function of Lingyang SPCE061A single-chip microcomputer is used to give voice prompts for faults that occur during the charging process, making the design more humane and easy to operate. The charging system can communicate with the host computer, thereby realizing networking between systems, which is conducive to the expansion of system functions. The system composition block diagram is shown in Figure 1.

　　1.2 Design of LCD display circuit

　　The display part uses ACM12864C LCD display, which is low-priced. The controller is KS0107 and KS0108, with an operating temperature range of 0℃~50℃ and a storage temperature range of -20℃~70℃. It has its own negative voltage generation circuit, a single +5V power supply, a backlight, and can be directly interfaced with various microprocessors. Data read and write operations are not controlled by an external clock. It does not have a Chinese character library, and the duty cycle is 1/64. There are 20 pins for external interfaces. ACM12864C can fully meet the requirements of Chinese character display. Through necessary program design, the battery status can be displayed dynamically and in real time on the ACM12864 LCD display by collecting the constant current, constant voltage, floating charge and other signals of the charger during the charging process. The interface between SPCE061A and ACM12864 is shown in Figure 2.

　　1.3 Keyboard circuit and I/O circuit design

　　This system uses CPLD as the interface between the SPCE061A microcontroller and the charger to achieve I/O port expansion and complete the keyboard scanning function. The use of CPLD replaces some dedicated integrated circuits, reduces the complexity of the system, and improves the integration of the system. This system uses hardware circuits to complete the scanning of the keyboard. When a key is pressed, the internal state of the CPLD changes. After the key is popped up, the internal state is automatically processed by the CPLD and converted into the corresponding key value and sent to the output port for the microcontroller to take away the key value when scanning. Compared with software to determine the working state of the keyboard, this not only saves the storage space of SPCE061A, but also greatly improves the working speed of the system and better realizes real-time performance.

　　The CPLD uses EPM7128SLC84-15 from the MAX7000S series produced by ALTERA. The chip has 84 pins and is made using EEPROM technology. It contains 2,500 logic gates, 128 macro units, and the clock operating frequency can reach 151.5MHz. Through the integration of resources by CPLD, it is possible to use one CPLD to implement I/O circuits, hardware scanning and discrimination, etc., and optimize the hardware layout. If the function of the system needs to be changed, only the corresponding source code needs to be changed instead of the hardware structure, so it has great flexibility.

　　2 System Software Design

　　2.1 Main program design

　　The software part of this system is compiled by mixing C language and assembly language, so the program has the characteristics of powerful functions and complete design. The main program mainly completes the following functions:

　　(1) System initialization and parameter setting;

　　(2) Detection and display of three working states of the charger;

　　(3) Control the operation and stop of each charger and the selection of two charging modes: fast charging and normal charging;

　　(4) Determine the positive and negative polarity of the battery and automatically give a voice alarm when the polarity is reversed;

　　(5) The charger will automatically shut down when the battery is fully charged; voice alarm will be automatically issued when an abnormal situation occurs;

　　(6) Set the fast charging time.

　　The main program flow chart of the system is shown in Figure 3.

2.2 Voice playback program design

　　There are roughly two ways to implement the D/A conversion channel of SPCE061A in hardware. One is to directly use the digital/analog converter DAC method, and the other is to use the pulse width modulation PWM drive method. The structure of the SPCE061A audio output is composed of two DAC channels or one PWM drive channel. Both of these implementation methods are actually digital/analog conversion, which converts digital signals into current analog signals for output. The audio output of SPCE061A adopts a dual-channel analog/digital conversion method, that is, the digital signal is converted into a 3mA driven current analog signal output through a 10-bit DAC. The voice prompt output directly uses the DAC channel, and after the signal is amplified, it is output by the speaker. The voice playback flow chart is shown in Figure 4.

　　2.3 CPLD Programming

　　VerilogHDL is a hardware description language that describes the functions, signal connection relationships, and timing relationships of hardware circuits. It uses language programming to represent the functions and behaviors of logic devices and systems. It has the advantages of complete design technology, flexible methods, wide support, strong hardware description capabilities, independence from device processes, and easy sharing and reuse. Compared with VHDL, VerilogHDL is a very easy-to-master hardware description language, while mastering VHDL design technology is more difficult. Therefore, using VerilogHDL to design interface circuits can fully utilize the advantages of VerilogHDL in system-level hardware description.

　　CPLD implements two multiplexers and a keyboard scanning circuit. The functions of each port in the program are shown in Table 1. datain1 consists of 18-bit input ports datain1[0]...datain1[17], which are divided into 6 groups, each with 3 ports. rs consists of 3-bit ports rs[0], rs[1], and rs[2], which can represent up to 8 binary numbers (6 of which are used in this design) to represent the port selection bit. dataout1 consists of 3 bits dataout1[0], dataout1[1], and dataout1[2], which represent the output port. datain1, dataout1, and rs form a multiplexer to implement the input selection function. The value of rs determines which group of datain1 signals is sent to dataout1 and output by dataout1. datain2 consists of datain2[0] and datain2[1], which represent the input port. dataout2 consists of 12-bit output ports dataout2[0]...dataout2[11], which are divided into 6 groups, each with 2 bits. Similarly, datain2, dataout2, and rs form another multiplexer to realize the output selection function. The value of rs determines which group of dataout2 the 2-bit signal of datain2 is output from. rt is a control pulse. When it is a rising edge, it realizes the input selection function, and when it is a falling edge, it realizes the output selection function. datain3 is a 16-bit key input port (low level is valid), and each bit represents a key. dataout3 is a 4-bit key value output port. When a key is pressed, the internal state of the CPLD changes. After the key is released, the internal state is automatically processed by the CPLD and converted into the corresponding key value and output from dataout3 (high level is valid). For example, when the datain3 bit is 1111111111111101, it means that key 2 is pressed, and dataout3 will output 0010, indicating that the key value is 2.

　　3 CPLD Simulation

　　From the initial circuit design idea to the waveform simulation of QuartusII and then to the end of CPLD chip programming, the development and design flow chart is shown in Figure 5.

　　On the QuartusII platform, after compiling the VerilogHDL program, use Simulator to perform timing simulation on it and obtain the result shown in Figure 6.

　　It can be seen from the figure that all the predetermined functions have been realized. For example, when datain3 is 111111011111, the output of dataout3 is 0110. The simulation results fully meet the requirements of the circuit.

　　The electric bicycle charging system designed based on SPCE061A+CPLD simplifies the system hardware and software design, improves the stability and reliability of the circuit, makes the system design flexible, shortens the development cycle, and makes it more integrated. At the same time, it makes the system easy to upgrade and expand. After inspection and testing, all technical indicators have met the design requirements.