Optimized Design of Digital Three-Phase Phase-Locked Loop Based on FPGA

Abstract: Digital three-phase phase-locked loops contain a large number of multiplication and trigonometric operations, which occupy a large amount of hardware logic resources. To this end, an optimized implementation scheme for digital three-phase phase-locked loops is proposed, which uses multiplication module reuse and CORDIC algorithm to realize trigonometric operations, and encodes the algorithms before and after optimization using Vetilog HDL hardware description language. Simulation and experimental results show that the optimized digital three-phase phase-locked loop greatly saves FPGA resources, can quickly and accurately lock the phase, and has good performance.
Keywords: FPGA; three-phase phase-locked loop; multiplication reuse; CORDIC

0 Introduction
In the control of power electronic devices that need to be connected to the grid, such as PWM rectifiers, uninterruptible power supplies (UPS), and active power filters (APF), obtaining the phase of the grid voltage is a prerequisite for system control. Generally, a phase-locked loop PLL is used to obtain the phase of the grid voltage. The three-phase grid voltage may have three-phase imbalance, and the voltage has harmonics, frequency, and phase mutations. In order to fully reflect the real situation of the grid voltage, a three-phase phase-locked loop is used to lock the grid voltage phase angle, and the three-phase phase-locked loop has stronger anti-interference ability. The field programmable gate array (FPGA) is used to implement the three-phase phase-locked loop in hardware, which can fully reflect the high speed of FPGA hardware and is not restricted by CPU resources.
This paper studies the system principle and algorithm implementation of the digital three-phase phase-locked loop, and optimizes the algorithm implemented in the FPGA. By using multiplication module multiplexing and the coordinate conversion module containing trigonometric functions based on the coordinate rotation digital computer (CORDIC) algorithm, the hardware overhead required for the implementation of the digital three-phase phase-locked loop is saved. The entire three-phase phase-locked loop system is designed using the hardware description language Verilog HDL. The three-phase phase-locked loop is verified on an experimental board with Altera's chip CyconeⅡEP2C15AF256C8 as the main chip.

1 Basic principles of three-phase phase-locked loop
1.1 Basic principles of phase-locked loop
The phase-locked loop is generally composed of a phase detector (PD), a loop filter (LF), and a voltage-controlled oscillator (VCO). The phase-locked loop is a phase feedback system. The phase detector compares the periodic input signal with the phase signal fed back by the VCO to obtain a phase error; the error is filtered by the loop filter, and the output of the loop filter is used as a control signal to the VCO to eliminate the phase difference between the input and output signals.
1.2 Structure and principle of three-phase phase-locked loop
The topology of the three-phase phase-locked loop is shown in Figure 1.

The key modules of the digital three-phase phase-locked loop are the two system transformations in vector control: the Clarke transformation (C32) from the abc three-phase stationary coordinates to the α-β two-phase stationary coordinates and the Park transformation (Cdq) from the α-β two-phase stationary coordinates to the dq two-phase rotating coordinates (fundamental synchronous speed is ω0):
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Where: U is the effective value of the voltage.
When the phase-locked loop is not locked, the q component is an AC component, which is compared with the set component q*=0 to obtain a DC component, thereby completing the phase detection. The DC component then controls the voltage-controlled oscillator through a low-pass filter composed of a PI controller, and finally makes ω equal to ω0, the q component is 0, and the phase is locked.

2 System simulation of three-phase phase-locked loop
According to the topological structure of the three-phase phase-locked loop in Figure 1, a system simulation model is built in Matlab/Simulink. The three-phase voltage is 220 V, the sampling frequency is fs=5 kHz, and the center frequency of the voltage-controlled oscillator is f=50 Hz. Through simulation adjustment, Kp=0.02 and K1=0.001 are finally determined, so that the speed and accuracy of the phase-locked loop phase are optimized. Figure 2(a) is the simulation waveform of three-phase voltage ua, ub, uc within 0.05 s of the three-phase phase-locked loop; Figure 2(b) is the simulation waveform of ud, uq under two-phase rotating coordinates within 0.05 s of the three-phase phase-locked loop. The d-axis component stabilizes to 0 at about 0.01 s, that is, it reaches phase lock in 0.5 cycles; Figure 2(c) is the simulation waveform of the three-phase voltage a phase angle θ and the VCO output phase angle θ* within 0.05 s of the three-phase phase-locked loop. θ and θ* are basically completely coincident at 0.01 s, achieving phase lock. The results show that the three-phase phase-locked loop can quickly and accurately lock the grid voltage within 0.5 cycles.

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3 FPGA Design of Three-Phase Phase-Locked
Loop 3.1 FPGA Structure of Unoptimized Three-Phase
Phase-Locked Loop According to the topology and principle of the three-phase phase-locked loop in Figure 1, the basic hardware structure of the three-phase phase-locked loop is shown in Figure 3.
First, the three-phase voltage is discretized and processed into a 32-b signed number through sampling. After Clarke transformation and multiplication with the corresponding parameters, the components μα and μβ of the two-phase stationary coordinates are obtained. There are 5 multiplication operations and 3 addition operations. Then there is Park transformation. In this three-phase phase-locked loop, only the μq component is required, which requires 2 multiplication operations, 2 trigonometric function calculations, and 1 addition operation. The subsequent PI controller requires 2 multiplication operations and 2 addition operations. Finally, the VCO requires 2 addition operations. The entire operation process requires a total of 9 multiplication operations, 9 addition operations, and 2 trigonometric function operations.
From the analysis of the basic structure of the three-phase phase-locked loop, it can be seen that the entire process requires 9 multiplication operations and 2 trigonometric function operations. Implementing multiplication operations and trigonometric function operations in FPGA will consume a lot of resources. In particular, the traditional lookup table method of trigonometric function operation consumes a lot of resources and has accuracy problems.
3.2 Optimization design of three-phase phase-locked loop
Since the design uses a 25 MHz system clock and a sampling frequency of 5 MHz, the timing margin of the design is very large. Based on the basic principle of balance and interchange between area and speed, multiplication multiplexing is adopted to achieve time division multiplexing by reasonably selecting the characteristics of more multiplication operations.
The trigonometric function operation in the Park transform can be optimized by the CORDIC algorithm. The CORDIC algorithm replaces multiplication and trigonometric function operations with basic addition and shift operations, which is particularly suitable for vector rotation operations. Using an iterative method, the angle to be rotated is completed in multiple steps. The CORDIC algorithm can implement the operation shown in formula (6).

In the formula: x0, x1 are the initial coordinates; θ is the angle to be rotated; y0, y1 are the final coordinates. By comparing the analysis of formula (6) with the Park transform, it can be found that as long as the angle is negative, the entire Park transform operation can be completed by the CORDIC algorithm.
The hardware structure of the optimized system is shown in Figure 4.

4 Conclusion
This paper analyzes the basic principle of three-phase phase-locked loop. The phase-locked loop is optimized according to the characteristics of FPGA and implemented using Verilog HDL hardware description language coding. This design can be directly used in control systems such as PWM rectifiers and UPS.