Real-time compression storage method of minefield reconnaissance images based on dual DSP

1 Introduction

With helicopters (manned or unmanned aircraft) as platforms, using visible light imaging and infrared imaging sensor technology, long-distance, large-area minefield reconnaissance and other obstacle system reconnaissance can be carried out day and night. When the airborne minefield reconnaissance system performs tasks, the system performs GPS calibration on the received minefield images, and compresses, stores and transmits the calibrated images in real time. The system has extremely high real-time requirements. Therefore, it is considered to use dual DSP and complex programmable logic devices (CPLD) as the core in the system to build a high-speed processing system. On the one hand, the use of dual DSP architecture can enable the system to have extremely high computing processing speed to meet real-time requirements. On the other hand, the introduction of CPLD has greatly improved the flexibility of the system. Combining the two can make the system fully reflect the faster and more flexible characteristics of the new generation of image compression systems.

2 Features of TMS320C62XX series DSP

According to the characteristics of the image compression and storage system, the TMS320C62xx series fixed-point DSP of Texas Instruments (TI) is used as the core processor. Its main frequency is 200 MHz~300 MHz, and its data processing capacity is 1600 MI/s~2400 MI/s. Its main features are as follows:

(1) The DSP core uses a very long instruction word (VLIW) architecture. The eight functional units share 32 32-bit general registers and can execute up to eight 32-bit instructions simultaneously in one cycle,
greatly improving the execution speed of the program.

(2) The circuit integrates 1 Mbit to 7 Mbit on-chip SRAM, which is divided into internal program/cache memory and internal data/cache memory. There is no bus competition and access speed mismatch between on-chip memory and external memory. Therefore, the access speed is fast and the powerful data processing capability of DSP can be fully utilized.

(3) It has a 32-bit external memory interface (EMIF) with an addressable space of up to 52 MByte. It can be seamlessly connected with SDRAM and SBRAM for large-capacity and high-speed storage. Its direct asynchronous memory interface can be connected with SRAM and EPROM for small-capacity data storage and program storage.

3 System Hardware Design

According to the functions, the image compression and storage system includes image acquisition module, GPS data acquisition module, CPLD logic control module, dual-port RAM + dual DSP image processing module, image real-time storage module and compressed data output module.

To meet the real-time requirements of the system, the entire system is designed to use three DSPs, one of which is used for real-time storage of compressed data, and two DSPs that work in cascade mode are used for real-time compression and transmission of minefield images. The system structure is shown in Figure 1.

DSP1 receives the minefield image data generated by the imaging device and the positioning data generated by the GPS positioning system, calibrates the minefield image according to the GPS positioning data, and then compresses the calibrated image in real time. DSP2 quantizes, reorders, sources and channels the compressed minefield image in sequence, and sends the encoded image to the ground through the data transmitter. DSP3 is mainly responsible for controlling the real-time storage of compressed data. [page]

3.1 Image acquisition module

This system uses the EMIF of DSP1 shown in Figure 1 to realize the communication with the visible light imaging sensor and the infrared imaging sensor, and collects the visible light image and infrared image information of the minefield. Since the EMIF interface of DSP1 is 32 bits, and the input word width of the image data is 8 bits, in order to make full use of the resources of DSP and make the system meet the requirements of fast transmission and processing, four 8-bit asynchronous FIFO memories are used between the sensor and DSP1 as the input buffer of the image data during the design. The hardware interface between FIFO and EMIF is shown in Figure 2.

The control logic in Figure 2 is implemented by CPLD1 in Figure 1. CPLD1 controls the generation of EMIF chip select signal (CEn), asynchronous output enable signal (AOE), asynchronous write enable signal (AWE), and asynchronous read enable signal (ARE) according to the timing required by the system, and generates DSP interrupt signals (INTx, INTy, INTz) by receiving the empty flag (EF), full flag (FF), and half-full flag (HF) of the FIFO, thereby realizing the read and write operations of the four asynchronous FIFOs.

3.2 GPS data acquisition module

The minefield images captured by various optical devices must be calibrated with the corresponding geographic coordinate information to make them meaningful. Therefore, the input data of the system should include the corresponding GPS positioning data in addition to the minefield image data.

The GPS positioning data calculated by the GPS positioning system based on the pseudo-range differential positioning principle is output in full seconds, and the output interface is an RS-232 serial interface. The TMS320C62xx series DSP has three multi-channel buffered serial ports (McBSP0-McBSP2). Considering the difference between the electrical characteristics of the McB-SP serial port and the RS-232 serial port, an RS-232 transceiver is connected to the McBSP interface of the DSPI during design to realize serial communication and receive GPS positioning data.

3.3 CPLD logic control module

In order to coordinate the efficient operation of each independent functional circuit in the system, two complex programmable logic devices (CPLDs) are used to control the access to the multi-segment memory space inside the DSP and manage the access timing between the DSP and the dual-port RAM and FIFO.

In addition, since the data output word width of the optical device is 8 bits and TTL level, while the DSP's EMIF interface is 32 bits and LVTTL level, the CPLD must also solve the problems caused by the interface differences between the optical device and the DSP by controlling the corresponding interface circuits, thereby ensuring the orderly and efficient operation of the entire system. [page]

3.4 Dual-port RAM + dual-DSP image processing module

As the core of the image compression and storage system, the image processing module uses dual DSPs as the core computing unit, and is supplemented by dual-port RAM to achieve high-speed communication between the two DSPs. The interface design between the external memory interface EMIF of the two DSPs and the dual-port RAM is shown in Figure 3. The dual-port RAM in the figure uses a 32-bit asynchronous RAM.

In the two DSPs shown in FIG3 , the functions of DSP1 are as follows:

• Receive raw minefield image data and GPS positioning data;
• GPS calibration of minefield image data;
• Store the GPS-calibrated images on the hard disk via EXBUS;
• The fast discrete cosine transform (FDCT) is used to compress the GPS-calibrated minefield images in real time.
• The compressed data is transmitted to DSP2 through the external memory interface EMIF and the dual-port RAM.
• The main functions of DSP2 are as follows:
• Receive compressed data from DSPI through external memory interface EMIF and dual-port RAM;
• Quantize and rearrange the compressed data;
• Performing source and channel coding on the compressed data after quantization and rearrangement;
• The encoded data is sent to the receiving station through the data transmission equipment.

The dual-port RAM, which serves as a high-speed communication bridge between the two DSPs, is a shared multi-port memory. It is equipped with two sets of independent address lines, data lines, and control lines, allowing two independent DSPs to asynchronously access the storage unit at the same time, thereby realizing the sharing of stored data and greatly improving the communication speed between the two DSPs.

The access arbitration logic inside the dual-port RAM manages the read and write operations of the two DSPs on the dual-port RAM by controlling the timing of access to the same address unit, reasonably allocating access rights to storage unit data blocks, and orderly scheduling signaling exchange logic (such as interrupt signals), thereby realizing orderly access of DSPI and DSP2 to shared data in the memory.

Although the two DSPs can communicate at high speed through the dual-port RAM, their control function is not strong. Therefore, the system needs to use two CPLDs as shown in Figure 1 to coordinate DSP1 and DSP2's access to the shared data in the dual-port RAM, so as to realize the calibration, compression, storage and transmission of minefield image data in real time and quickly.

3.5 Image Storage Module

The original image data is stored after GPS calibration as a backup of the minefield image data received on the ground. Since the minefield data captured by the optical device has the characteristics of low altitude, high speed and high ratio, and high resolution, it is a massive amount of data, so it must be stored on a hard disk. In order to avoid conflicts in the internal hardware resources of the DSPI shown in Figure 1, the EXBUS of the DSPI is used as the interface for the output of the image storage data.

The minefield image data calibrated by GPS is first output to the FIFO buffer through the EXBUS interface of DSP1, and then the compressed data is stored on the hard disk through the DMA controller and the interface controller respectively. The control of the hard disk uses DSP3 and a dedicated SCS1 interface controller to realize data storage. The hardware interface between EXBUS and asynchronous FIFO is shown in Figure 4.

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3.6 Compressed Data Output Module

After the minefield image data marked by GPS is compressed using a specific algorithm, it must be transmitted to the ground for later analysis and processing. After the compressed data is encoded by DSP2, it is transmitted to the FIFO buffer through the EMIF of DSP2, and then sent to the data transmission device through the bus driver to the ground receiving station. The FIFO memory uses the IDT72V06 asynchronous FIFO memory, and the bus driver uses the HC245 bus driver of SGS-THOMSON.

4 Image Compression Algorithm Design

The efficiency of the image compression algorithm directly affects the real-time performance of the entire system. Therefore, choosing a suitable image compression algorithm is of vital importance.

The system adopts an image compression algorithm based on FDCT transform, which can achieve a high compression ratio under the condition of good image quality, and the calculation amount is moderate, which can meet the requirements of real-time image compression. Its software flow is shown in Figure 5. The algorithm in the upper virtual box in Figure 5 is executed by DSP1, and the algorithm in the lower virtual box is executed by DSP2, and the intermediate data is transmitted through the dual-port RAM.

Since the compressed data has very low redundancy, the RoI (Restart of Interval) marker must be appropriately inserted during source coding to enhance the error resistance of the compressed data and avoid error propagation.

In addition, in order to improve the reliability of communication, channel coding should be added to the coding. Considering the good forward error correction capability and real-time performance of convolutional codes, convolutional codes are selected as channel coding. Theoretically, the longer the constraint of convolutional codes, the better the error correction capability, but the longer the constraint, the longer the decoding time. Therefore, when designing, it is necessary to start from real-time performance and select the appropriate convolutional code constraint to ensure that the error rate correction capability of the data transmission equipment can meet the system's real-time, reliability and anti-interference requirements.

5 Conclusion

The system uses the fast data processing capability of the TMS320C62xx series DSP and the high-speed data transmission capability of the dual-port RAM to quickly calibrate the large-area minefield images taken by the optical sensor with GPS, and compress, store and transmit the calibrated images in real time, thus meeting the real-time requirements of the airborne large-area minefield reconnaissance system.