On August 30, Microsoft attended the Hot Chip 2024 conference and shared the specifications of the Maia 100 chip. Maia 100 is one of the largest processors manufactured on TSMC's 5nm node and is designed specifically for large-scale AI workloads deployed in Azure.
The Maia 100 chip specifications are as follows:
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Chip size: 820 mm2
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Package: TSMC N5 process using COWOS-S sandwich technology
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HBM BW/Cap;1.8TB/s @ 64GB HBM2E
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Peak dense Tensor POPS: 6bit: 3,9bit: 1.5, BF16: 0.8
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L1/L2:500MB
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Backend network BW: 600GB/s (12X400gbe)
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Host BW (PCIe): 32GB/s PCIe Gen5X8
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Design TDP: 700W
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Provision TDP:500W
The Microsoft Maia 100 system is vertically integrated to optimize cost and performance. It also uses a custom server board with a specially designed chassis and software stack to improve performance.
Maia 100 Architecture
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The high-speed Tensor unit provides high-speed processing for training and inference while supporting multiple data types. The unit adopts a 16xRx16 structure.
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The vector processor is a loosely coupled superscalar engine with a custom instruction set architecture (ISA) that supports multiple data types including FP32 and BF16.
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The direct memory access (DMA) engine supports different tensor sharding schemes.
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Hardware semaphores support asynchronous programming of Maia systems.
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To improve data utilization and power efficiency, large L1 and L2 scratch pads are managed by software.
Maia 100 uses Ethernet-based interconnect technology and custom protocols like RoCE to enable ultra-high bandwidth computing. It supports up to 4800 Gbps of all-gather and scatter-reduced bandwidth, and 1200 Gbps of all-to-all bandwidth.
On the software side, the Maia software development kit (SDK) allows anyone to quickly port their PyTorch and Triton models to Maia. The Maia SDK provides developers with several components that enable them to easily deploy models to the Azure OpenAI service.
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