Software decoding and hardware decoding methods for motor position sensors

Regarding the topic of motor position sensors, the following two questions are often asked, which are briefly sorted out here:

What is "hardware decoding"?

What is "software decoding"?

The resolver position sensor has 6 lead connectors, namely: input (excitation +, excitation -), output (sine +, sine -, cosine + and cosine -).

From the calculation formula of the rotary transformer we introduced, we can know that:

Excitation input: Ve=Esin(ωt)

Sine output: V1=K* Esin(ωt)*sinθ

Yuxuan output: V2=K* Esin(ωt)*cosθ

Among them, θ is the resolver rotor angle; ω is the excitation carrier frequency; E is the excitation input peak voltage; K is the conversion ratio.

Figure 1. Correspondence between various signals of the resolver

1. Resolver "hardware decoding": Resolver-digital conversion chip RDC

The conventional decoding scheme is to use a resolver-to-digital converter chip RDC to directly connect to the resolver sensor, as shown in Figure 2. The analog signal (sine and cosine signals) output by the resolver is decoded in hardware to obtain the angular position signal and speed signal of the resolver rotor. This scheme is commonly known as "hardware decoding". Commonly used RDC chips include AD2S90, AD2S1200, AU6802/ZSZ/XSZ-014, etc.

Figure 2. Resolver-to-digital converter chip RDC decoding architecture

The signal of the resolver is converted into a digital value in the RDC chip: position information, and the speed is determined by counting the number of pulses in a specific time window. The RDC decoding process is shown in Figure 2. The oscillator generates an excitation voltage (about 8kHZ, 10Vrms) to power the resolver position sensor, and the resolver outputs positive and cosine signals in the RDC chip. After passing through the cosine multiplier, sine multiplier and a comparator, the following is obtained:

△V=K* E*sin(ω*t)*sinθ*cosβ- K* E*sin(ω*t)*cosθ*sinβ

    After simplification, we can see that:

 △V=K* E*sin(ω*t)*sin(θ-β)

   Among them, β is the angle corresponding to the counter;

△V then enters the synchronous rectifier and is demodulated with the excitation signal to remove the carrier frequency ω. The resulting difference voltage signal is proportional to sin(θ-β), that is:

△V'=A* sin(θ-β)

△V' then enters the integrator. When there is a difference between the angles θ and β, the integrator will output a DC voltage signal, which will be input into the voltage-controlled oscillator VCO to generate a pulse signal, and finally enter the up/down calculator. The sine/cosine multiplier, synchronous rectifier, integrator, voltage-controlled oscillator, calculator and D/A converter form a closed-loop control system, similar to the phase-locked loop PPL. When the difference between the angles θ and β is 0, the digital value of the counter corresponds to the angle analog value output by the resolver position sensor, and the RDC chip decoding is completed.

During the continuous rotation of the resolver, the VCO generates pulses until the count value of the counter corresponds to the analog value of the rotor angle at the input, that is, the offset of the resolver rotor angle. At the same time, the frequency of the voltage-controlled oscillator is proportional to the speed of the resolver rotor, so the output voltage of the integrator can be output as a speed signal.

**2. ****Resolver "software decoding": **Digital signal processing and software technology

At present, most of the electric drive resolver decoding of new energy vehicles adopts the combination of CPU processor, FPGA/CPLD and software technology. Compared with the resolver-digital conversion chip RDC decoding, it is mainly based on the following considerations:

• ASIC that meets functional safety requirements;

• Reduce costs and eliminate RDC chips;

• The hysteresis effect of speed is eliminated, digital filters are used, and bandwidth conversion is realized by software to compromise the relationship between bandwidth and resolution, and make bandwidth a function of speed;

• Improved the ability to resist environmental noise;

  The following will introduce the resolver "software decoding" by taking a digital processor resolver software decoding architecture that meets functional safety requirements as an example, as shown in Figure 3. The resolver output sin+/- and cos+/- signals are processed by the "comparator" to obtain single-ended sin/cos signals, which enter low-pass filtering and then undergo AD conversion and are sent to the FPGA and CPU respectively.
  The FPGA will generate the resolver excitation voltage signal and process the sin/cos signals to calculate the rotor angle and speed; at the same time, the CPU will also process the sin/cos signals to calculate the rotor angle and speed, and verify them with the FPGA calculation results. In addition, the CPU will also monitor the FPGA's processing of the resolver's input/output signals.

Figure 3. Digital processor resolver software decoding architecture

The calculation of the rotor position angle using the Luenberger observer is shown in Figure 4:

Figure 4. Luenberger observer calculates angle

Figure 5. Signal correspondence of the Luenberge observer calculating the angle

The rotor angle is calculated by the inverse tangent algorithm, as shown in FIG6 , and is used to compare and verify the rotor position angle calculated by the Luenberger observer.