Design of an Adaptive Spectral Line Enhancement System Based on FPGA

0 Introduction

In signal acquisition and processing, we often only care about signals with narrow bandwidth and strong periodic characteristics. At this time, broadband noise becomes a harmful component that must be filtered out. The spectrum of the signal carries the most essential characteristics of the source, but the actual acquired signal is inevitably affected by broadband noise or broadband interference. How to quickly and efficiently eliminate these noises and interferences and enhance the target spectrum line is of great significance in the field of signal processing. ALE uses the periodicity of narrowband signals and the weak correlation of broadband noise to adaptively extract signals from noise under the condition of unknown signal characteristics, and is widely used in target recognition and feature extraction. FPGA occupies an important position in the field of digital signal processing due to its high design flexibility, high-speed data processing capabilities, and rich on-chip resources. Here, FPGA is used as the core part of digital signal processing. Pipeline structure and distributed algorithm are effective ways to fully utilize the high-speed processing capabilities of FPGA and realize complex digital signal processing algorithms. The core part of ALE constructs an FPGA pipeline structure that uses the LMS (Least Mean Square LMS) algorithm to achieve adaptive spectrum line enhancement and hardware implementation.

1 Adaptive filtering principle

Adaptive filtering is relative to fixed filters. The filtering frequency of fixed filters is fixed, while the filtering frequency of adaptive filters automatically adapts to the input signal, so its application range is wider. Adaptive filters are the best filters that meet certain criteria. This kind of filter can automatically update its weight coefficients according to the changes of the input signal without any prior statistical knowledge about the signal and noise to meet the needs of optimal filtering. Adaptive filters can process not only stationary random signals but also non-stationary random signals. These characteristics make adaptive filters widely used in signal processing fields such as interference elimination, prediction, inversion, and identification.

The principle of adaptive filtering includes two aspects: one is the adaptive algorithm for adjusting the filter coefficients, and the other is the filter structure. The adaptive filtering algorithm is to set a certain criterion so that the difference between the output signal after filtering and the reference signal is minimized under this criterion. The Wiener criterion is widely used in adaptive filtering, and its solution is the Wiener solution. The filter structure is a way to specifically implement the adaptive algorithm, and seeking an efficient filter structure has always been the research focus of adaptive filtering. The FIR lateral structure is the most common filter structure. Designing a pipeline for the hardware of the lateral structure filter is an effective way to implement high-speed adaptive filtering in FPGA. Therefore, the pipeline is used in this design to implement the adaptive filter of ALE. The principle of the adaptive filter is shown in Figure 1. Among them, x(n) is the input signal, y(n) is the output signal, d(n) is the reference signal, and e(n) is the error signal.

The LMS algorithm is an easy-to-implement, robust, and widely used algorithm. It uses the negative error energy gradient to update the weight coefficients of the filter. Its steady-state solution is still the Wiener solution. The algorithm recursive formula is as follows:

Where: Xj is the input signal; Wj is the weight coefficient of the adaptive filter; dj is the reference signal; ej is the error; μ is a gain constant used to control the adaptive speed and stability.

2 ALE principle and its Matlab simulation

2.1 ALE Principle

ALE belongs to the category of adaptive filtering, but in the design of adaptive filters for spectral line enhancement, there is no external reference signal available. At this time, the original input signal is connected to a delay line with a fixed delay as a reference signal, taking advantage of the fact that the narrowband signal has obvious periodicity and the broadband noise has poor periodicity. After a period of delay, the correlation function of the narrowband signal will be significantly stronger than the broadband noise. As long as the selected delay △ is long enough, the correlation between the broadband noise of the reference signal and the broadband noise of the original input will weaken rapidly, while the correlation of the narrowband periodic signal will not be affected. According to the theory of adaptive filtering, ALE filtering will have a learning process, and the learning process is the process in which the error signal tends to decrease continuously. When the learning process enters a steady state, the filter output is the source narrowband periodic signal and a random error, and the error can reach a very small amplitude by selecting a suitable step size factor. The ALE schematic is shown in Figure 2.

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2.2 Matlab simulation of ALE

Matlab is an effective tool for digital signal processing and simulation. Using Matlab for simulation at the beginning of the design can effectively evaluate the final effect of the design and provide strong theoretical support for the entire design process. First, Matlab is used to simulate the ALE implemented by the LMS algorithm. The effectiveness of the algorithm in the ALE system is proved from the time domain waveform and processing time of the simulation results. The sine wave mixed with Gaussian white noise is used as the input signal of the spectral line enhancement filter. Figure 3 is a partial simulation result of the algorithm using Matlab. It can be seen that the original periodic signal cannot be judged at all according to the input signal mixed with noise. After the learning process of 0 to 100 time length, the output signal of the filter has obvious periodicity, the broadband noise is effectively filtered out, and the narrowband signal is filtered out. This period of time only requires μs processing time in high-speed FPGA, which meets the real-time requirements.

3 System Structure

The ALE system generally includes: analog/digital conversion, FPGA core processing, off-chip RAM, power supply, etc. The front end uses TLC5510 to complete the acquisition of analog signals and transmits them to FPGA in the form of digital signals. The FPGA part is the core of the entire system, which realizes the timing control of analog/digital converter, internal data cache FIFO, on-chip clock synthesis, spectral line enhancement algorithm and off-chip RAM control. The data after spectral line enhancement is stored in the off-chip RAM chip CY7C1021V. The power supply provides the 3.3 V and 5 V required by the entire system and the reference voltage of TLC5510. The system structure is shown in Figure 4.

TLC5510 is a high-speed analog/digital converter from TI, which can be used in video processing, high-speed data conversion and other fields. Its conversion rate reaches 20 Mb/s. The high-speed AD chip is used to match the high-speed processing capability of FPGA. EP2C8F256C6 is a CycloneⅡ series FPGA produced by Altera. It has 162 Kb of on-chip memory and 36 18×18 b on-chip multipliers, which can be used to implement complex digital signal algorithms. The on-chip memory is based on the popular M4K memory block and can support a wide range of configurations, including RAM, ROM, first-in first-out (FIFO) buffers, and single-port and dual-port modes. On-chip multipliers are ideal for low-cost digital signal processing (DSP) applications. These multipliers can be used to implement general DSP functions such as finite impulse response (FIR) filters, fast Fourier transforms, correlators, encoders/decoders, and numerically controlled oscillators (NCOs). EP2C8F256C6 provides advanced external memory interface support, allowing developers to integrate external single data rate (SDR), double data rate (DDR), DDR2 SDRAM devices and second generation 4x data rate (QDRⅡ) SRAM devices. The chip has a clock management module, which uses PLL to realize on-chip clock synthesis, so that the data processing rate is much higher than the signal acquisition rate to meet the real-time requirements. The sampling control of TLC5510 is first implemented inside the FPGA. The sampling signal must first be stored in the on-chip FIFO. After each ALE algorithm iteration is completed, the data in the FIFO is taken out and the processing data is updated. The data to be processed is processed by signal delay processing and LMS adaptive filtering algorithm to obtain a spectral enhanced signal. The on-chip clock synthesis module provides the clock signal for the system, and uses the on-chip PLL to multiply and divide the crystal oscillator clock to provide a 600 MHz clock inside the chip and a 10 MHz clock for the off-chip TLC5510 and RAM. In order to ensure data accuracy. The data processed by ALE is output as a 16-bit binary digital signal. The off-chip memory uses a 64K×16b static RAM chip CY7C1021V, and its read/write control timing is also implemented by FPGA.

3.1 Control of TLC5510

TLC5510 is an 8-bit high-speed analog-to-digital converter that performs sampling in a pipeline mode. It starts and completes one sampling in each clock cycle. Sampling is performed on the falling edge of the clock, and the conversion result is output after 2.5 clock cycles. In the design, the sampling control process is described by a state machine according to the sampling timing, and the sampling control is realized. The VHDL code for implementing state alternation is as follows:

The VHDL code for implementing sampled data output is as follows:

3.2 Sampling Signal Delay

In order to achieve delay, three buffers are opened in the FPGA chip, namely input, delay, and weight buffers. The sampled data is first stored in the on-chip data cache FIFO and enters the standby state. The delay buffer implements a delay of length △, and the weight buffer stores the weights. Among them, the addresses of the delay buffer and the input buffer are continuous. The length of the delay buffer is determined by the delay △, and the length of the input buffer and the weight buffer is determined by the dimension of the weight. The implementation of the buffer is to define the vectors for storing data in the program written in VHDL language. The data types of these data vectors are defined as follows:

Among them: ARRAY_N1BIF defines the data type of the filter parameter vector; ARRAY_N1BIYX defines the data type of the delayed signal vector; ARRAY_N1BIT defines the data type of the input signal vector; ARRAY_N2BIT defines the data type of the signal vector after spectral line enhancement; W1 is the width of the sampling data, which is 8 here; Delay is the delay length; L is the filter order.

3.3 LMS algorithm core module

This is the core part of the design and also the difficulty in the design. Implementing complex digital signal processing with FPGA is not as simple as in DSP. It is necessary to consider timing synchronization, data width and how to round. This design uses a 16-order adaptive filter to implement ALE. The initial weights of the filter are all 0. It is iteratively updated according to the algorithm of formula (3). A large number of multiplication operations are used in the algorithm implementation. Calling the multiplier macro function module lpm_mult embedded in the chip makes it faster and more efficient to implement these multiplication operations. The lpm_mult module inputs the sampled 8-bit data. Because the result of multiplying two 8-bit binary numbers in the multiplication operation is a 16-bit binary number, the design outputs the processing result as a 16-bit binary number. In order to improve the speed of adaptive filtering, the design adopts a pipeline filter structure. The pipeline structure can significantly improve the processing speed, but it consumes more hardware resources, especially hardware multipliers. If the length of the LMS FIR filter is L, 2L general multipliers are required. In the design, L=16, and there are 36 on-chip multipliers in the chip to meet the processing requirements. The compilation results show that the other resource consumptions used in the LMS core algorithm are all less than or equal to 6% of the total consumption, and the remaining resources can be used for timing control such as sampling and output in the chip. The pipeline structure block diagram of the hardware implementation of the LMS algorithm is shown in Figure 5.

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The VHDL code for calling the multiplier in the pipeline structure is as follows:

4 Simulation Results Analysis

Some simulation results of the VHDL program on QuartusⅡ software are shown in Figure 6, where the simulation data is expressed in decimal. Because the simulation results are not easy to draw similar graphics in Matlab, the data of the simulation results are compared with the Matlab simulation results. Through line comparison, it is found that the processing results are generally consistent with Matlab, but there is some overall attenuation in amplitude. This is because the low bits of the processing results are truncated in the FPGA, while the Matlab simulation environment uses floating point form and has a long data bit number. The processing accuracy is much higher than that of FPGA, and there is a large truncation error in FPGA design. The simulation results show that it is feasible to implement ALE based on FPGA.

5 Conclusion

The system uses FPGA chip plus a small amount of peripheral circuits to complete the adaptive spectral line enhancement of the signal. By calling the FPGA on-chip multiplier and on-chip memory, the adaptive spectral line enhancement of the LMS algorithm is completed, and the simulation results are consistent with the theory. Most modern digital signal processing algorithms require a large number of multiplication operations. Calling the FPGA on-chip multiplier is a fast, efficient and economical means to implement these algorithms, which makes it possible to implement complex signal processing algorithms on FPGA. The pipeline structure is an effective means of sacrificing resources to increase speed in hardware design. Effective use of the pipeline can significantly improve resource utilization and processing speed. This design can achieve high-speed and accurate spectral line enhancement, which has certain practical significance in the field where broadband noise needs to be filtered out to extract a single spectral line.