Research and Design of PCI Bus Interface Principle Based on FPGA

In modern data acquisition and processing systems, expansion buses such as ISA, EISA, and MCA can no longer meet the requirements of high-speed data transmission, while the PCI local bus has become the mainstream bus for most systems due to its excellent cost-effectiveness and adaptability.

PCI bus features

The PCI bus width is 32 bits and can be upgraded to 64 bits; the maximum operating frequency is 33MHz, and it supports burst operation to increase the transmission speed; low random access delay (the write access delay from the master register to the slave register on the bus is 60ns); the processor/memory subsystem capabilities are completely consistent; an implicit central arbitrator; the multiplexing architecture reduces the number of pins and PCI components; PCI expansion boards for ISA, EISA, and MAC systems reduce users' development costs; PCI expansion cards and components can be automatically configured to achieve plug-and-play of devices; the processor is independent, does not rely on any CPU, supports multiple processors and future higher-performance processors; supports 64-bit addresses; multi-master control allows point-to-point access between any PCI master device and slave device; PCI provides parity checking for data and addresses to ensure data integrity and accuracy.

Current Status of PCI Interface Development

At present, there are generally two ways to develop PCI interfaces. One is to use a dedicated PCI interface chip, which can realize the complete interface functions of the PCI master module and the target module, and convert the complex PCI bus interface into a relatively simple user interface. Users only need to design the converted bus interface, which shortens the development cycle. The disadvantage is that users may only use part of the PCI interface functions, which causes a certain waste of logic resources and lacks flexibility. It is likely to increase the components on the board, resulting in an increase in product costs and a decrease in reliability. The second is to use programmable devices. The advantage of using FPGA lies in its flexible programmability. First, the PCI interface can be optimized according to the card function without having to implement all PCI functions, which can save the system's logic resources. Moreover, users can integrate other user logic on the PCI card with the PCI interface logic on one chip to achieve a compact system design. When the system is upgraded, only the logic design of the programmable device needs to be redesigned without updating the PCB layout. Now more and more users are using programmable devices such as FPGA and CPLD to develop PCI devices.

The PCI interface controller discussed in this article works as a conversion interface between the PCI bus and the user device. It can also be considered that its main function is to act as a bridge to complete the information transmission between the user device and the PCI bus.

PCI interface design

In the design of PCI board, the core design consists of two parts: timing control and configuration space. Timing control ensures that the board can work according to the normal PCI timing, and the configuration space part ensures the plug-and-play function of the board. When designing FPGA, the software used in this design is Altera's MAX+PLUSII, and the development chip is EPF10K20RC240-3.

● Implementation of PCI interface configuration space

The PCI bus defines three physical address spaces: memory address space, I/O address space, and configuration address space.

Configuration space is a space unique to PCI. Its purpose is to provide a set of appropriate configuration measures to meet the current and foreseeable system configuration mechanism. Configuration space is an address space with a length of 256 bytes and a specific record structure. It can be accessed when the system boots or at other times. The space is divided into two parts: the header area and the device-related area. The device only needs to implement the necessary and related registers in each area. The base address register of the configuration space provides a mechanism to specify storage space or I/O space for the device. The operating system When starting up, it needs to determine how much memory is in the system and how much address space is required for the I/O devices in the system. Then, based on the results, it automatically configures the system's storage space and I/O space to achieve device-independent management. In this design, those read-only configuration registers are wired to the corresponding values ​​through hardware, so they do not occupy macro units. Through the configuration registers, the configuration software can understand the existence, functions and configuration requirements of the target device.

(1) Manufacturer ID: This 16-bit read-only register defines the manufacturer of the device. The ID value 1022 of AMD, the original manufacturer of the MACH chip, can be used.

(2) Device ID: This value is assigned by the manufacturer to identify its product and can be any value except 00000000H and 0FFFFFFFFH.

(3) Command register: This register controls the device's ability to respond to PCI accesses. Bits 1, 6, and 8 are implemented in this design. This design requires access to storage space. When bit 1 is set to 1, the device responds to PCI access to memory; bit 6 controls the device's response to parity errors; when bit 8 is set to 1, the device can drive the SERR line, and 0 disables the device's SERR output driver. Here, when the system is reset, bits 1, 6, and 8 are set to 0.

(4) Status register: This register records information about PCI related events. In this system, bits 9, 10, 11, 14, and 15 are designed and implemented. Bits 10:9 are device select (DEVSEL#) timing, 00B for slow, 01B for medium, 10B for fast, and 11B reserved. In this design, these two bits are hardware wired to 01B. When the target device fails, bit 11 is set to 1, when a system error occurs, bit 14 is set to 1, and when a parity error occurs, bit 15 is set to 1.

(5) Base address register: This register is used to map the device's memory address space. The low bits corresponding to the size of the device address space are forced to 0. Therefore, in a configuration write transaction, the configuration software determines the address range occupied by the device memory by writing 1 to all bits of this register and then reading the value of this register. Bit 0 is used to define whether the device is memory mapped or I/O mapped. In this design, bit 0 is set low to indicate that the target device is memory mapped.

If 256 bytes of storage space is needed, the configuration software writes 0FFFFFFFFH, and this device sends 0FFFFFF00H. The value written by the configuration software to the base address register again and the result of ANDing with 0FFFFFF00H of this device is the base address value. For example, if the configuration software writes 0CD000000H again, the base address value is 0CD000000H.

(6) Class Code Register: This 24-bit read-only register is used to describe the basic functions of the device and its programmable interface. Here, this register is forced to 018000H, which means that the device is a mass storage controller.

(7) Header Type Register: Bits 0 to 6 of this read-only register define the header format, and bit 7 indicates whether the device is single-function or multi-function. Header Type 1 is defined for PCI-PCI bridges, and Header Type 2 is used for PCI CardBus bridges. In this design, the register is forced to 0 to indicate that it is a single-function device and the header type is 0. [page]

● Timing control

The state machine model is used in the timing control program to realize the conversion of different timings. Various commands, data exchanges, and controls are all managed by the state machine. The signals on the PCI bus work in parallel, so the tasks to be performed must be clearly defined for each state. These tasks use VHDL process statements to describe the events that occur. The state machine in this design uses a total of 6 states, which are based on the response status of the slave device, mainly based on the status of the DEVSEL# signal and the TRDY# signal. The state machine is shown in Figure 1, which corresponds to the idle state (in this state, DEVSEL#, TRDY#, STOP# and other output signals are in high impedance state); the ready state, DEVSEL# and TRDY# are both high-level states, DEVSEL# is low-level and TRDY# is high-level state, DEVSEL# and TRDY# are both low-level states; the operation end state (this state makes DEVSEL#, TRDY# and STOP# maintain a high level for a cycle). After receiving the reset signal, this system resets the system and then enters the idle state. In the idle state, the bus is sampled and the state machine is determined to which state after the next clock rising edge based on the changes in the bus. The signals used in these timing sequences and programs are basic and necessary. Necessary states and signals can be added as needed during development. The VHDL description of the state machine is as follows.

type pci_state is (Idle, Ready, DevTrdyHi, DevLoTrdyHi, DevTrdyLo, OprOver);

signal c_state :pci_state;

Idle is the idle state; Ready is the ready state; DevTrdyHi means that DEVSEL# and TRDY# are both in the high level state; DevLoTrdyHi means that DEVSEL# is in the low level and TRDY# is in the high level state; DevTrdyLo means that DEVSEL# and TRDY# are both in the low level state; OprOverr means the operation end state.

The procedure is as follows.

The next step is to list the concurrent events corresponding to each state and write the related processes. A process statement is a parallel statement that defines the specific behavior to be performed when the process is activated. For example, in the Ready state, it is necessary to determine whether the address information sent from the master device is the same as the slave device address, so an address comparison process must be written. [page]

address_compare: process (pci_rst, pci_clk), the main content is to decode the address and determine whether the address is in the slave device space. If it is in this space, the next step can be taken, otherwise no other action is taken.

From the above analysis process, we can get the following design ideas: sample FRAME#, address and command on the rising edge of the clock. If FRAME# is valid, decode the address and command. If the bus command is 011x and the address on the bus is within the target address range, it indicates that this is an operation on the memory of this device; or if the bus command is 101x and the IDSEL signal is valid, it indicates that this is an operation on the configuration space of this device. In both cases, determine whether it is a read operation or a write operation based on the last bit of the bus command, and use the DEVSEL# and TRDY# signals to start data transmission; and sample the FRAME# and IRDY# signals during the transmission process to confirm the last data cycle, and invalidate the DEVSEL# and TRDY# signals to end data transmission.

Through the above design, one set of simulation results in the MAX+PLUSII environment is shown in Figure 2.

Conclusion

This article gives a design scheme for designing PCI bus interface using FPGA technology on PCI bus. This technology can be used to make your own algorithm technology and some software into hardware and solidify it on the card, which not only improves the running speed but also protects intellectual property rights.