Xilinx Launches Vivado® ML Edition to Power Machine Learning

Xilinx (NASDAQ: XLNX) introduced Vivado® ML Edition, the industry's first FPGA EDA tool suite based on machine learning (ML) optimization algorithms and advanced design flows for team collaboration, which can effectively save design time and cost. Compared with the current Vivado HLx version, Vivado ML Edition reduces the compilation time of complex designs by 5 times, while also providing a breakthrough average of 10% improvement in the quality of results (QoR).

Figure: Xilinx's new Vivado® ML version

“Today’s EDA designers are challenged by increasing design complexity, and machine learning is the next big leap in accelerating the design process and improving QoR,” said Nick Ni, director of software and AI solutions marketing at Xilinx. “Vivado ML will help developers shorten design cycles and deliver a new level of productivity from design creation to closure.”

Machine Learning-Based Optimizations
Vivado ML Edition supports machine learning-based algorithms to accelerate design closure. The technology features machine learning-based logic optimization, delay estimation, and intelligent design execution, which automatically executes strategies to reduce timing closure iterations. 

“The new Vivado ML edition’s intelligent design runtime is a game changer,” said Robert Atkinson, principal hardware engineer at National Instruments. “It proactively improves timing results with a one-click approach, generates QoR recommendations that deliver the greatest impact, and provides expert quality results by reducing user analysis, especially for hard-to-converge designs.”

Faster compilation time and productivity for team collaboration
Xilinx also introduced the concept of Abstract Shell, which allows users to define multiple modules within the system and compile them incrementally and in parallel. Compared with traditional full-system compilation, this approach can speed up the average compilation time by 5 times, and up to 17 times. The abstract shell can also hide design details outside the module, thus helping to protect the customer's IP, which is critical for FaaS (FPGA-as-a-Service) and value-added system integrators.

In addition, Vivado ML improves collaborative design with Vivado IP Integrator, enabling modular designs using the new Block Design Container (BDC) feature. This feature promotes a design approach for team collaboration and allows a divide-and-conquer strategy to handle large designs with multiple sites working together.

Xilinx's unique adaptive features such as Dynamic Function Exchange (DFX) can dynamically load custom hardware accelerators remotely at runtime to more efficiently utilize chip resources. DFX's ability to load design modules in milliseconds opens up many new use cases, such as vehicles switching between different vision algorithms while processing frame data, or genomic analysis switching between different algorithms in real time during DNA sequencing.

Vivado ML Edition is available now in free Standard and Enterprise editions, starting at MSRP $2,995.