Getting started and improving Vivado (high runner-up)

This course introduces in detail the use of Xilinx's new generation development platform Vivado. It is divided into two parts: introductory part and advanced part; it covers four major topics: design process, timing constraints (XDC), design analysis and the use of Tcl scripts; attached Multiple project demos. The design concept of Vivado "IP Centric" runs through it, and the demo shows the powerful functions of Vivado and the differences from ISE.

• Chapter 1：Vivado design process and usage patterns (17 minutes and 48 seconds)

• Chapter 2：Use three DEMOs to explain how to use IP in design (31 minutes and 34 seconds)

• Chapter 3：Logic simulation based on XSim (24 minutes and 12 seconds)

• Chapter 4：Logic simulation based on ModelSim (DEMO project file is consistent with Lecture 3) (8 minutes and 25 seconds)

• Chapter 5：Comprehensive basic settings and comprehensive properties (32 minutes and 3 seconds)

• Chapter 6：accomplish (27 minutes and 26 seconds)

• Chapter 7：incremental implementation (22 minutes and 43 seconds)

• Chapter 8：The 5 most commonly used Tcl commands in Vivado (39 minutes and 50 seconds)

• Chapter 9：Programming and Debugging (31 minutes and 24 seconds)

• Chapter 10：Input, output and clock planning (21 minutes and 56 seconds)

• Chapter 11：Some tips related to Vivado design process (26 minutes and 34 seconds)

• Chapter 12：Basic concepts and terminology in timing analysis (24 minutes and 43 seconds)

• Chapter 13：Create basic clock cycle constraints (32 minutes and 21 seconds)

• Chapter 14：Set input delay constraints (21 minutes and 56 seconds)

• Chapter 15：Set output delay constraints (14 minutes and 32 seconds)

• Chapter 16：virtual clock (14 minutes and 37 seconds)

• Chapter 17：Set multi-cycle path constraints (17 minutes and 21 seconds)

• Chapter 18：Set pseudo path (15 minutes and 24 seconds)

• Chapter 19：constraint priority (17 minutes and 7 seconds)

• Chapter 20：Comprehensive design analysis (1): resource and fan-out analysis (19 minutes and 18 seconds)

• Chapter 21：Design analysis after synthesis (2): Timing analysis (20 minutes and 45 seconds)

• Chapter 22：UltraFast Design Methodology (1): First introduction to UltraFast (12 minutes and 0 seconds)

• Chapter 23：UltraFast Design Methodology (2): Clock (17 minutes and 47 seconds)

• Chapter 24：UltraFast Design Methodology (3): RTL Code Style (1) (17 minutes and 3 seconds)

• Chapter 25：UltraFast design methodology (4): RTL code style (2) (14 minutes and 41 seconds)

• Chapter 26：UltraFast Design Methodology (5): Timing Constraints (16 minutes and 41 seconds)

• Chapter 27：UltraFast Design Methodology (6): Define Clock Grouping (18 minutes and 6 seconds)

• Chapter 28：UltraFast Design Methodology (7): How to Manage IP Constraints (12 minutes and 30 seconds)

• Chapter 29：UltraFast Design Methodology (8): Using Design Rule Checking in Vivado (15 minutes and 6 seconds)

• Chapter 30：UltraFast Design Methodology (9): Understanding Implementation Strategies (22 minutes and 59 seconds)

• Chapter 31：UltraFast Design Methodology (10): Basic principles of timing constraints for timing closure (19 minutes and 12 seconds)

• Chapter 32：UltraFast Design Methodology (11): 10 Timing Closure Techniques for Timing Closure (25 minutes and 38 seconds)

• Chapter 33：Power consumption estimation and optimization (21 minutes and 14 seconds)

• Chapter 34：Design and develop with Vivado IP Integrator (18 minutes and 5 seconds)

• Chapter 35：Application of Tcl in Vivado (1): Editing the netlist (21 minutes and 23 seconds)

• Chapter 36：Application of Tcl in Vivado (2): Customized reports (20 minutes and 57 seconds)

• Chapter 37：Application of Tcl in Vivado (3): Using Hook Script (15 minutes and 4 seconds)

• Chapter 38：Application of Tcl in Vivado (4): Embedding custom Tcl commands (12 minutes and 55 seconds)

• Chapter 39：Application of Tcl in Vivado (5): Using Xilinx Tcl Store (9 minutes and 33 seconds)

• Chapter 40：Application of Tcl in Vivado (6): Design process management in engineering mode (22 minutes and 3 seconds)

• Chapter 41：Application of Tcl in Vivado (7): Design process management in non-engineering mode (16 minutes and 16 seconds)