cotex m4 assembly instruction set

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cotex m4 assembly instruction set [Copy link]

16-bit data operation instructions Name Function ADC Addition with Carry (ADD with Carry) ADD Addition AND Bitwise AND. The bitwise AND function here is the same as the "&" function in C ASR Arithmetic Shift Right BIC Bitwise clear (bitwise AND a number with the complement of another unsigned number) CMN Negative comparison (compare a number with the binary complement of another data) CMP Compare (Compare, compare two numbers and update the flag) CPY Copy (COPY) the value of one register to another EOR Near Bitwise Exclusive OR LSL Logical Left Shift LSR Logical Right Shift MOV Register loads data, which can be used for both transfer between registers and for loading immediate data MUL Multiplication MVN Load the NOT value of a number (get the logical inverse value) NEG Get the two's complement ORR Bitwise OR ROR Rotate right SBC Subtraction with borrow SUB Subtraction TST Test (Test, perform a bitwise AND operation and update Z based on the result) REV Reverse the byte order in a 32-bit register REVH Split a 32-bit register into two (Half) 16-bit numbers and reverse the byte order in each 16-bit number REVSH Reverse the byte order of the lower 16-bit halfword of a 32-bit register and sign-extend it to 32 bits SXTB Signed byte extension to 32 bits SXTH Signed half word extension to 32 bits UXTB Unsigned byte extension to 32 bits UXTH Unsigned half word extension to 32 bits 16-bit transfer instructions Name Function B Unconditional branch B  Conditional transfer BL transfer and link. Used to call a subroutine, the return address is stored in LR CBZ Compare, if the result is zero (Zero) then jump (can only jump to the following instruction) CBNZ Compare, if the result is non-zero (Non Zero) then jump (can only jump to the following instruction) IT If-Then 16-bit memory data transfer instructions Name Function LDR Load (Load) a word from memory into a register (Register) LDRH Load half (Half) word from memory into a register LDRB Load byte (Byte) from memory into a register LDRSH Load half word from memory and store it in a register after sign extension LDRSB Loads a byte from memory and stores it in a register after sign extension STR Stores a register as a word into memory STRH Stores the lower halfword of a register into memory STRB Stores the lower byte of a register into memory LDMIA Loads multiple words and increments the base register after loading STMIA Stores multiple words and increments the base register after storing PUSH Pushes multiple registers onto the stack POP Pops multiple values from the stack into registers Other 16-bit instructions Name Function SVC System Service Call BKPT Break Point instruction. If debugging is enabled, enter the debugging state (halt). NOP No Operation CPSIE Enable PRIMASK (CPSIE i)/FAULTMASK (CPSIE f) - Clear the corresponding bit CPSID Disable PRIMASK (CPSID i)/FAULTMASK (CPSID f) - Set the corresponding bit 32-bit Data Manipulation Instructions Name Function ADC Add with Carry ADD Addition ADDW Wide Addition (Can add 12-bit immediate data) AND Bitwise AND ASR Arithmetic Right Shift BIC Clear a bit (complement a number bit by bit and then add it to another number logically) BFC Clear a bit segment BFI Insert a bit segment CMN Compare negatively (compare a number with the binary complement of another number and update the flag) CMP Compare two numbers and update the flag CLZ Count the number of leading zeros EOR Bitwise Exclusive OR LSL Logical Shift Left LSR Logical Shift Right MLA Multiply and Add MLS Multiply and Subtract MOVW Put a 16-bit immediate number into the bottom 16 bits of a register and clear the upper 16 bits MOV Load 16-bit immediate value into register (actually the assembler will generate MOVW - translator's note) MOVT Put 16-bit immediate value into the upper 16 bits of a register, the lower 16 bits are not affected MVN Move the two's complement of a number MUL Multiplication ORR Bitwise OR (the original text is logical OR, incorrect - translator's note) ORN Invert the source operand bit by bit, and then perform a bitwise OR (the original text is logical OR, incorrect - translator's note) RBIT Bit reversal (first express a 32-bit integer in binary, then rotate it 180 degrees - translator's note) REV Reverse a 32-bit integer byte by byte REVH/REV16 Perform a 32 4]REVSH Reverse the low halfword of a 32-bit integer and sign-extend it to a 32-bit number ROR Round right shift RRX Logical right shift with carry (the highest bit is filled with C and does not affect the value of C) SFBX Extract an arbitrary bit range from a 32-bit integer and sign-extend it to a 32-bit integer SDIV Signed division SMLAL Signed multiply and add long (multiply two signed 32-bit integers to get a 64-bit signed product and add the product to another signed 64-bit integer) SMULL Signed long multiplication (multiply two signed 32-bit integers to get a 64-bit signed product) SSAT Signed Saturation Operation SBC Subtraction with Borrow SUB Subtraction SUBW Wide Subtraction, can subtract 12-bit immediate value SXTB Byte Sign Extension to 32-bit Number TEQ Test for Equality (Performs XOR on two numbers, updates flags but does not store result) TST Test (Performs bitwise AND on two numbers, updates Z flag but does not store result) UBFX Unsigned Bit Segment Extract UDIV Unsigned Division UMLAL Unsigned Multiply and Accumulate Long (Multiply two unsigned 32-bit integers to obtain a 64-bit unsigned product, and then add the product to another unsigned 64-bit integer) UMULL Unsigned long multiplication (multiply two unsigned 32-bit integers to get a 64-bit unsigned product) USAT unsigned saturation operation (but the source operand is signed - translator's note) UXTB bytes are unsigned extended to 324]LDRD Load doubleword (64-bit integer) from a contiguous address space into two registers STR Store word from a register STRB Store low byte from a register STRH stores the lower halfword of a register STM stores words from several registers to a continuous address space STRD stores doublewords consisting of 2 registers to a continuous address space PUSH pushes the values of several registers into the stack POP pops the values of several registers from the stack 32-bit transfer instructions Name Function B Unconditional transfer BL Transfer and connect (call subroutine) TBB Table lookup transfer in byte units. Select an 8-bit forward jump address from a byte array and transfer TBH Table lookup transfer in half-word units. Select a 16-bit forward jump address from a halfword array and jump to it Other 32-bit instructions LDREX loads a word into a register and marks an address in the kernel as being in exclusive access LDREXH loads a halfword into a register and marks an address in the kernel as being in exclusive access LDREXB loads a byte into a register and marks an address in the kernel as being in exclusive access STREX checks if the address to be written has been in exclusive access and if so stores the word in the register STREXH checks if the address to be written has been in exclusive access and if so stores the halfword in the register STREXB checks if the address to be written has been in exclusive access and if so stores the byte in the register CLREX Clears the exclusive access status flag on the local process (the flag previously set by LDREX/LDREXH/LDREXB) MRS Loads the value of a special function register into a general register MSR Stores the value of a general register into a special function register NOP No operation SEV Send event WFE Sleeps and wakes up when an event occurs WFI Sleeps and wakes up when an interrupt occurs ISB Instruction synchronization isolation (related to pipeline and MPU, etc. - translator's note) DSB Data synchronization isolation (related to pipeline, MPU and cache, etc. - translator's note) DMB Data storage isolation (related to pipeline, MPU and cache, etc. - translator's note)Send events WFE sleeps and wakes up when an event occurs WFI sleeps and wakes up when an interrupt occurs ISB instruction synchronization isolation (related to pipelines and MPU, etc. - translator's note) DSB data synchronization isolation (related to pipelines, MPU, cache, etc. - translator's note) DMB data storage isolation (related to pipelines, MPU, cache, etc. - translator's note)Send events WFE sleeps and wakes up when an event occurs WFI sleeps and wakes up when an interrupt occurs ISB instruction synchronization isolation (related to pipelines and MPU, etc. - translator's note) DSB data synchronization isolation (related to pipelines, MPU, cache, etc. - translator's note) DMB data storage isolation (related to pipelines, MPU, cache, etc. - translator's note)