Design of intelligent control unit for circuit breaker based on DSP+CPLD

　　hardware design

　　TMS320F2812DSP Introduction

　　TMS320F2812DSP is a 32-bit high-performance digital signal processor launched by Texas Instruments (TI). It has a peak processing speed of 1.5 million instructions per second (MIPS) and a single-cycle 32×32-bit MAC operation function. It also has 128k×16 on-chip Flash, 18k×16 on-chip RAM and a large number of on-chip peripherals, including A/D conversion module, 2 event managers (EVA and EVB), CAN bus controller, 2 serial communication interface modules (SCIA and SCIB), serial peripheral interface module (SPI), multi-function serial interface (McBSP) and 56 general-purpose I/O ports.

　　DSP uses the efficient 32-bit fixed-point CPU TMS320C28xTM as the core processor, and its development can use either C28x assembly or ANSI C/C++ language. In addition, TI also provides virtual floating-point math function library (IQ math function library), fast Fourier transform (FFT) algorithm function library, filter library, etc. These function libraries can significantly simplify application system development. The powerful functions of TMS320F2812 enable it to meet the design requirements of embedded intelligent control units.

　　System hardware design

　　The main tasks of the intelligent control unit include: processing the control commands of the main control module, monitoring the bus power parameters, temperature acquisition, implementation of the protection control algorithm, detecting the state of the switch quantity, output control of the switch quantity and communication with the monitoring center. In order to achieve the above functions and make full use of the powerful peripheral functions of DSP TMS320F2812 and the advantages of the embedded operating system, DSP mainly completes analog quantity acquisition, data processing, algorithm implementation, temperature acquisition, communication and command processing. At the same time, in order to quickly detect the state and the reliability of the output execution signal, CPLD will complete the monitoring of the state quantity, communication with DSP, output of the state signal and control of the external high-voltage circuit. The system structure is shown in Figure 1. The design of the system hardware includes the design of various conditioning circuits, CAN bus communication drivers, RS-232 bus drivers and RS-485 bus drivers and the internal circuits of CPLD.

Figure 1 Intelligent control unit system structure diagram

　　Conditioning circuit design

　　The conditioning circuit includes AC voltage acquisition conditioning circuit, switch quantity acquisition conditioning circuit, and switch quantity control drive circuit. AC voltage signal acquisition uses F2812

It has a built-in 12-bit A/D conversion module, which has a sample-and-hold circuit and requires an input voltage range of 0~3V. Therefore, an isolation circuit consisting of a voltage transformer, a current-voltage conversion circuit and an RC filter and a conditioning circuit consisting of an amplifier, a voltage booster, a voltage follower and a limiter are designed to convert a 220V/50Hz voltage signal into a 0~3V voltage signal.

　　The acquisition of switch quantity is realized by CPLD. Since the switch quantity often has jitter problems, its conditioning circuit needs to take measures to remove the switch jitter. In its conditioning circuit, capacitor C is used to filter out the peak voltage in the input signal (mainly for high-frequency interference), and the 12V voltage regulator diode is used to filter out the interference signal (mainly for low-frequency interference). The photocoupler is to prevent the external signal from affecting the operation of the internal circuit; the diode VD is used to protect the light-emitting diode in the optical coupler to prevent the light-emitting diode from being reversely broken down. The switch quantity control signal is output through the I/O pin of the CPLD. The output signal drives the external high-voltage device to operate through the optical coupler device TLP127.

　　Since the intelligent control unit is mainly used to control the closing of the circuit breaker, and a strong electromagnetic effect will be generated during the closing process of the circuit breaker, if it is directly driven by the GPIO pin of the DSP, external electromagnetic interference may cause the DSP program to run away or reset the DSP, seriously affecting the execution results. Therefore, the input/output of the switch quantity in the system is completed by CPLD, and its reliability will be enhanced.

　　Communication Module

　　F2812 has an enhanced CAN controller eCAN module, which fully supports the CAN2.0B protocol. Its performance is greatly improved compared with the existing DSP embedded CAN controller. When communicating on the CAN bus, data transmission is more flexible and convenient, with larger data volume, higher reliability and more complete functions. Therefore, this design uses the CAN bus to realize the communication of intelligent terminals. The hardware design of the communication module is mainly the design of the CAN bus drive circuit. Philips' CAN communication transceiver PCA82C250 is selected as the interface between the CAN controller and the physical bus of F2812 to realize the differential sending and receiving functions of the bus. To prevent the introduction of interference signals, the design uses high-speed optocoupler 6N137 to isolate F2812 and the physical bus. The RS-232 driver chip directly uses the MAX232 driver chip, while the RS-485 driver chip uses the SNLBC184. At the same time, in order to prevent interference signals from entering, the design uses the optocoupler TLP521 to isolate F2812 and RS-232 and RS-485 bus driver chips. 　　CPLD module design

　　In this intelligent control unit, CPLD is an important component. The state acquisition and output execution system composed of CPLD can work independently, mainly controlling the asynchronous closing of the circuit breaker, accepting various input key operations and state input/output. During synchronous control, CPLD receives the action command transmitted by DSP, that is, it can execute the synchronous closing operation. At the same time, when the state changes, CPLD will send an interrupt signal, and DSP will read the state and make corresponding processing or transmit it to the monitoring center. The input signals of CPLD mainly include asynchronous closing, closing, and reset inputs, the position signal of the circuit breaker, the position signal of the switch trolley, the undervoltage tripping, the overcurrent tripping, the system voltage signal, etc. The function of its information output module is mainly to display whether the circuit breaker has the conditions for operation, the closing/opening state of the circuit breaker, the action execution of the circuit breaker, and the output control circuit breaker action command. The control block diagram of CPLD is shown in Figure 2. As a separate control execution mechanism, CPLD can generate corresponding operation circuits by writing corresponding VHDL codes, including latching, judging and processing of various input signals, as well as the execution of various command signals and the control of output signals.

　　software design

　　Software design includes system software design and application software design.

Figure 2 CPLD control block diagram

　　The main task of system software design is to realize the transplantation of μC/OS-Ⅱ on F2812; the main task of application software design is to realize system functions.

　　System software design

　　μC/OS

-Ⅱ Introduction

　　The system software of this design adopts the open source real-time operating system μC/OS-Ⅱ, which is a priority-based, portable, curable, customizable, preemptive real-time operating system. Most of its source code is written in ANSI C.

　　To use μC/OS-Ⅱ, you must first successfully transplant the kernel to the CPU you are using. The transplantation of μC/OS-Ⅱ on F2812 includes four contents.

　　a. Define processor-related constants, macros, and data types in OS_CPU.H. For example, the definitions of disabling interrupts and enabling interrupts are #defineOS_ENTER_CRITICAL() asm "DINT" and #defineOS_EXIT_CRITICAL() asm "EINT" respectively.

　　b. Adjust and modify the header file OS_CFG.H to reduce or modify the system services of μC/OS-Ⅱ and reduce resource loss. For example,

　　#defineOS_MBOX_EN0 prohibits the use of mailbox-related codes.

　　c. Write the C language file OS_CPU.C. Since several other functions are not used in this design, the main function here is to complete

　　Writing of OSTaskStkInit(). OSTaskStkInit() is used to initialize the task stack structure, making it look like an interrupt has just occurred and saving all registers to the stack.

　　d. Write the assembly language file OS_CPU.ASM. This file includes 4 sub-function programs: OSStartHighRdy() (run the highest priority task), OSCtxSw() (task switching at the task level), OSIntCtxSw() (task switching at the interrupt level) and OSTickISR() (μC/OS-Ⅱ time tick interrupt function). This is the key and difficult point in the μC/OS-Ⅱ transplantation. The reasonable implementation of these functions is the basis for ensuring the operation of μC/OS-Ⅱ.

　　After completing the above work, μC/OS-Ⅱ can run.

　　Application software design

　　According to the functional requirements of the intelligent control unit, the system is divided into 11 tasks and 3 interrupts, including AC voltage acquisition module, data processing module, circuit breaker action time prediction module, communication module, and interface module with CPLD. Each task is assigned a certain priority according to its real-time requirements and refers to the monotonic execution rate scheduling method RMS. The definition of tasks and interrupts is shown in Table 1.

　　The highest priority is the start task (TaskStart), which is the first task to run after the system starts. In this task, the system and related peripherals must be initialized, and necessary self-tests must be performed, and then the remaining tasks must be created. After the creation of the remaining tasks is completed, the task must delete itself and give system resources to other tasks, and the entire system will start to run normally. The schematic code of this task is as follows:

　　/*System and peripheral initialization*/
/*System self-test*/
/*Create each task*/
StartCpuTimer2(); /*Start time slice*/
OSStatInit(); /*Statistical task initialization*/
Create each application task of the intelligent control unit;
KickDog(); /*WatchDog reset*/
OSTaskdel(OS_PRIO_SELF); /*Delete start task*/
Except for TaskStart(), the structures of the other task modules are infinite loop bodies. Figure 3 shows the general task flow chart.

Figure 3 Task flow chart

　　Task communication and synchronization

　　μC/OS-Ⅱ provides five methods for data sharing and task communication: semaphore, mailbox, message queue, event flag and mutually exclusive semaphore. Semaphore can control the right to use shared resources, coordinate external events with the execution of tasks, and provide the fastest communication for inter-task communication, synchronization and mutual exclusion. μC/OS-Ⅱ provides three types of semaphores, namely binary, counting and mutually exclusive. Event flags can synchronize tasks with multiple events. If they are synchronized with any of multiple events, it is called independent synchronization; if they are synchronized with multiple events, it is called associated synchronization. Mailbox is a communication mechanism that can send a pointer variable that points to a data structure containing a specific message. Message queue is another communication mechanism that allows a task or interrupt service subroutine to send a variable defined by a pointer to another task. The specific application is different, and the data structure pointed to by each pointer is also different. Mutually exclusive semaphore is a special binary semaphore that is mainly used to solve the inherent mutual exclusion problem and reduce the priority flipping required in practical applications. When designing the intelligent control unit software, these communication mechanisms provided by μC/OS-Ⅱ are fully utilized to coordinate the operation of each independent task. 　　Implementation of communication protocol

　　F2812 provides a standard CAN2.0B bus protocol, which is a physical layer protocol. Because the intelligent control unit is used in power system control, the common application layer protocols of the power system are CDT, MODBUS, DNP3.0, etc. In the process of this design, the application layer protocol will adopt the MODBUS protocol. The implementation of the communication protocol is relatively complicated, but due to the use of a real-time operating system, the implementation of the communication protocol can be uniformly managed by the operating system, mainly completed by the tasks of receiving, sending, packaging, and unpacking data.

　　Summarize

　　a. The design uses a new high-performance DSPTMS320F2812 chip with multiple peripherals, which greatly reduces the workload of system hardware design and shortens the development cycle. The design adopts the method of separate design of DSP minimum system and conditioning circuit, and adopts multi-layer board structure in the design of DSP minimum system, and uses a large number of surface mount components to improve the stability and electromagnetic compatibility of the system.

　　b. As an embedded operating system based on priority scheduling,

The reasonable allocation of task priorities is crucial to the normal operation of the system. In this design, the allocation of task priorities first considers meeting the real-time performance of the system, and then considers the execution frequency of the task under the same conditions. Through repeated adjustments, the priority allocation table 1 is finally determined.

　　c. This project utilizes the execution circuit design based on CPLD. Due to the reliability and fast response of the internal hardware structure of CPLD, it is very suitable for power system control. Therefore, the use of full CPLD (or ACTELFPGA) should be a research direction.

　　d. As a new member of the 2000 series launched by TI, F2812 is still in the exploratory stage of development and design in China. The system design idea based on TMS320F2812+μC/OS-Ⅱ proposed in this article will play a certain role in promoting the study and use of F2812.