Study on the control strategy of a novel current source three-phase five-level converter topology

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Study on the control strategy of a novel current source three-phase five-level converter topology [Copy link]

Existing research on multilevel converters is mainly focused on voltage source converters[2](VSI for short), while research on current source converters[1](CSI for short) is relatively limited. This is not only because common power sources such as generators, power grids, and batteries are all voltage sources, but also because the energy storage element capacitor in VSI has obvious advantages over the energy storage element inductor in CSI in terms of energy storage efficiency, volume, and price. However, with the development of superconducting technology[3], the energy storage efficiency problem of inductors in current source converters will be solved. Compared with VSI, CSI also has its own characteristics. It is easy to realize four-quadrant operation, and its operation is more stable and its output current is easier to control. Therefore, it will be more and more widely used in active power filtering (APF), reactive power compensation (SVG) and power systems. For multilevel inverters, PWM technology is undoubtedly a solution to obtain ideal output. Generally speaking, the control strategy applicable to multi-level VSI is also applicable to multi-level CSI, but the appropriate control strategy should be adopted for different topologies. For combined multi-level CSI, each unit CSI is relatively independent in control, so it is easy to use PWM technology. For direct multi-level CSI, the conventional modulation method cannot be simply followed. Generally, the following factors must be considered when selecting the control strategy for three-phase multi-level CSI:

1) To maintain continuous conduction of DC current;

2) Ensure the current balance of the shunt inductor;

3) The mutual coupling effect of three-phase current should be taken into account.

1 Circuit topology analysis

Figure 1 shows the three-phase five-level CSI topology (hereinafter referred to as direct three-phase five-level) introduced in this article. Each switch device consists of a MOS tube and a fast recovery diode in series. In steady state, considering the symmetry of the circuit topology and ignoring the ripple of the inductor, a current source with a value of I/2 can be used to replace each current sharing inductor in the circuit analysis diagram. As shown in Figure 2, its output levels are -I, -I/2, 0, I/2, and I.

Figure 1 Three-phase direct five-level CSI topology

Figure 2 Three-phase direct five-level CSI equivalent circuit

The CSI in this article is two ordinary inverters connected in parallel at the two ends of the same current busbar, but its working principle is to use the idea of multi-level combination. The five-level topology uses four current-sharing inductors to divide the input current and output current of the inverter into two equal parts, and then uses the corresponding switches to reasonably distribute and combine the three-phase current to obtain the required five-level. Taking phase A as an example, the output level and switch conduction diagram are shown in Table 1.

Table 1 Schematic diagram of output current of phase A iA Open state (closed is 1, open is 0)


2 Research on modulation mode of three-phase direct five-level CSI

Commonly used PWM control methods for multi-level converters include: multi-level harmonic elimination PWM (SHPWM), carrier phase shift (CPS-SPWM), switching frequency optimization (SFO-PWM), and space vector modulation (SVPWM). The modulation mode of the three-phase new five-level CSI shown in Figure 1 in this paper is a combinational logic PWM technology, which uses three sinusoidal modulation signals with a phase difference of 120° and a triangular carrier for comparison (the amplitude of the sine wave is 5V, and the amplitude of the triangular wave is 2.5V), and then outputs the corresponding PWM wave through a combination of digital and analog circuits.

Figure 3 shows the digital solution used to implement PWM technology. All comparator units (determine the switching logic) receive three-phase sinusoidal modulation signals. Each sinusoidal wave corresponds to an EPROM and a D/A converter. Each EPROM is addressed by a different counter and synchronized with the power supply of the corresponding phase through a phase-locked loop. The amplitude control signal is Vmod, which is multiplied by the output of the EPROM containing the sinusoidal modulation signal after D/A conversion and then used as the modulation signal for each comparison module unit.

Figure 3 Digital PWM solution

For the current-type inverter circuit, the switching action must meet three conditions, namely, maintaining continuous conduction on the DC side; considering the influence of the mutual coupling of the three-phase current; and the average voltage on the current-sharing inductor should be zero. Based on the above considerations, this paper adopts the following PWM control strategy.

1) Taking phase A as an example, as shown in Figure 4 (a), a two-level pulse signal is obtained by comparing SINA and -SINA with the same triangular carrier, and the two signals are superimposed to obtain a three-level pulse signal PA. (Similarly, signals PB and PC can be obtained). The three-level pulse signals PA and PB are superimposed to obtain a set of five-level modulation signals PA-PB, as shown in Figure 4 (b). Similarly, PB-PC and PC-PA can be obtained.

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(a) Phase A decoupling control circuit (b) Control signal PA-PB

Figure 4 Generation of a set of three-level modulation signals (taking phase A as an example)

2) Considering the above current level combination conditions, PA1 (PA1, PA2, PA3, PA4 represent the control signals on switches SA1, SA2, SA3, SA4 respectively) is taken as the level signal greater than zero in the positive half cycle, PA2 is the level signal greater than I/2 in the positive half cycle, similarly, PA3 is the level signal less than zero in the negative half cycle, and PA4 is the signal less than -I/2 in the negative half cycle. Through the analog switch, PA1, PA2, PA3, and PA4 are evenly output alternately. In this way, the driving signal on each switch tube is a wide and narrow pulse width alternation, ensuring that the conduction time of the left and right bridge arms is consistent within several cycles, so as to better achieve the average voltage of the current-sharing inductor to be zero. As shown in Figure 5 (b), the driving signals of the three switches in the same bridge arm.

(a) Eliminate DC no-path logic circuit (b) Three switch control signals in the same bridge arm

Figure 5 Elimination of DC no-path logic circuit and three switch control signals in the same bridge arm

3) In this experiment, each bridge arm of the main circuit cannot have a DC no-path condition. In order to eliminate the DC no-path condition, taking one bridge arm as an example, the logic control shown in Figure 5 (a) is adopted to obtain a signal that the bridge arm is not conducting after the three switch signals on the bridge arm are "OR-N". This signal is "AND-ed" with the phase signal to which it belongs, and then "OR-ed" with the signal of the path to obtain the control signal on each switch tube. This can well ensure that each bridge arm of the main circuit does not have a DC no-path condition.

3 Direct three-phase five-level CSI simulation and experiment

3.1 Simulation parameters and results

To verify the correctness of this control strategy, this paper simulates the three-phase five-level CSI composed of the new topology. The simulation parameters are as follows: the current source current is 20A, each current sharing inductor is 100mH, the output operating frequency of the inverter is 50Hz, the load resistance is 8Ω, the load is star-connected without a neutral line, and the output filter is composed of LC combination (L=5mH, C=60μF).

Figure 6(a) shows the output PWM current waveform of the three-phase five-level CSI. Figure 6(b) shows the three-phase load current waveform after filtering. It can be seen that the filtered current waveform is very close to a sine wave.

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(a) Output PWM current (b) Load current after filtering

Figure 6 Simulation waveform

3.2 Experimental parameter results

Based on the previous analysis and discussion, the three-phase direct five-level CSI topology was experimentally verified. The main circuit of the experiment is shown in Figure 1, and the parameters are as follows: each current-sharing inductor is 100mH, the frequency of the output current is 50Hz, the load resistance is 8Ω, the output filter capacitor is 60μF, the filter inductor is 8mH, and the carrier ratio is 32. The experimentally measured input current is about 4A. Figure 7 (a) shows the three-phase load current waveform before filtering, and Figure 7 (b) shows the waveform after filtering. It can be seen that the output waveform is very close to a sine wave.

(a) Three-phase load waveform before filtering (b) Three-phase load waveform after filtering

Figure 7 Experimental waveform (10V/div

, 5ms/div, the current waveform is the voltage waveform taken on the resistive load)

4 Conclusion

The direct CSI multilevel inverter is a very unique topology. With the breakthrough development of high-temperature superconducting technology and its practical application, superconducting technology will solve the energy storage efficiency problem of energy storage inductors in current-source converters [3]. At the same time, the energy storage coil in the power superconducting energy storage system has the characteristics of a current source. Therefore, the current-source converter will have a wide range of application prospects. It is of great significance to study the topology and control of three-phase direct CSI.