Three power supply requirements analysis solutions for FPGA power requirements

Currently, more and more home appliances are migrating from low-speed dial-up Internet access to broadband Internet access or Internet Protocol Television (IPTV), and IPTV is expected to develop rapidly in China. In comparison, the infrastructure cost of IPTV is quite low because this method does not require copper coaxial cables, but uses DSL or broadband links and set-top boxes to deliver program streams to home appliances.

Today’s field-programmable gate arrays (FPGAs) have proven to be ideal for this platform because they offer the flexibility to rapidly change market demands. FPGA power requirements are often complex because FPGAs have up to three power supply requirements that must be sequenced to achieve reliable system performance.

Core voltage

The core voltage rail is usually set to VCCINT, which powers the FPGA logic. The current required ranges from a few hundred milliamps to tens of amps, depending on the clock frequency and the number of gates used. Because this load is highly capacitive, the core voltage current requirement may be high at the beginning. The FPGA core has strict requirements for transient response, and the core supply voltage must be increased slowly and often required to rise to a stable voltage within a fixed length of time. For example, Xilinx's Virtex-4 must power up the VCCINT supply between 0.2ms and 50ms.

I/O Voltage

I/O voltage (VCCIO) typically requires a voltage rail of 3.3V, 2.5V, 1.8V, or 1.5V. I/O standards can be set independently by the I/O modules in the FPGA, so it is possible for an FPGA to have more than one I/O voltage. The I/O current requirement depends on the number of I/Os used and the clock speed. Typically, the I/O current requirement is low, ranging from a few hundred mA to 3A.

Auxiliary voltage

The auxiliary voltage (VCCAUX) requires a power supply with a high power supply rejection ratio (PSRR) because the supply is directly connected to the digital clock management (DCM). If power supply noise is allowed to couple into the DCM, it may affect the performance of the system.

Although the I/O and auxiliary voltages do not need to be powered up in a particular order, FPGA manufacturers often specify or track the power-up sequence for the core and I/O. The consequences of not specifying or tracking the power-up sequence are often irreparable damage to the devices in the system. FPGAs, PLDs, DSPs, and microprocessors often place diodes between the core and I/O power supplies as ESD protection elements. If the power supplies violate the tracking requirements and exceed the forward bias of the protection diodes, the device may be damaged.

Solution

To illustrate the complexity of FPGA power supply requirements, take the requirement for VCCINT to be powered on within a fixed time period as an example. In order to ensure the power-on time between 2ms and 50ms controlled by the upper and lower limits, the circuit shown in Figure 1 is implemented.

Figure 1: MIC37302 and discrete circuitry ensure controlled slope and timing

The power-up sequencing or power-up sequence tracking of the core and I/O power supplies increases the complexity and cost of the power management circuit. To overcome this problem, design engineers need a device that meets all these needs without adding external components. An example of such a product is Micrel's MIC68200 LDO, which is suitable for various on-board power supplies. It integrates the functions of rise speed control, power-up sequencing and tracking into a 3×3mm MLF package.

Multiple MIC68200s can be cascaded in two modes: in tracking mode, the output of the master device drives the RC pin of the slave device so that the slave device tracks the master regulator during turn-on and turn-off; in sequential power-on mode, the POR of the master device drives the enable (EN) terminal of the slave device so that it turns on after the master device turns on and turns off before (or after) the master device turns off. In addition to the tracking capability, the voltage ramp control (RC) pin can also accurately program the ramp voltage of the core voltage rail through a capacitor. [page]

The tracking and sequencing circuits are shown in Figures 2 and 3 respectively. It can be seen from the figures that the solution is a simple implementation that requires very few discrete components.

Figure 2: Tracking circuit, the core voltage ramp is set by the capacitor on the RC pin

Figure 3: Sequencing circuit. The master regulator’s POR enables the slave regulator. The POR delay is set by a low capacitor.

Conclusion

In summary, the benefits of using FPGA as an encoding and decoding platform in IPTV video broadcasting are obvious. However, powering the FPGA can be a challenge, and using dedicated power management devices designed according to power requirements, such as the MIC68200, will greatly shorten the time to market for new systems.