Solution of digital amplitude-frequency balanced power amplifier based on FPGA

Abstract: A design scheme of digital amplitude-frequency balanced power amplifier based on FPGA is proposed. Based on the design of the front-stage small signal amplifier circuit based on AD620, the amplitude-frequency characteristics of the stopband network are analyzed; the corresponding filter composition scheme is given by combining the analysis results with the FIR filtering algorithm. The rear-stage power amplifier circuit is implemented with discrete MOS tubes.

In modern communication systems, inter-symbol interference is an important factor that restricts communication quality. In order to reduce inter-symbol interference, it is necessary to compensate the channel appropriately to reduce the bit error rate and improve communication quality. The compensator in the receiver that can compensate or reduce the inter-symbol interference of the received signal is called an equalizer. This paper proposes a solution for a digital amplitude-frequency equalized power amplifier based on FPGA.

1 Overall system design

This paper designs a scheme for implementing a digital signal amplitude-frequency balanced power amplifier. The design mainly consists of four modules: small signal amplification, band-stop network attenuation, digital signal amplitude equalization, and power amplification. The small signal amplification part is implemented by the AD620 operational amplifier with high precision and low noise coefficient; the digital signal processing part uses FPGA as the processing core, assisted by A/D and D/A modules for the conversion of analog and digital signals; the final power amplifier circuit is implemented by discrete MOS tubes.

2 Hardware Circuit Design

2.1 Preamplifier circuit design

The preamplifier uses the low-power, high-precision instrumentation amplifier AD620[3], and inserts a variable resistor between pins 1 and 8 of the amplifier to achieve gain control, so as to meet the requirement of the question that the amplification factor is not less than 400 times. The preamplifier circuit is shown in Figure 1. According to the internal structure of AD620, its gain expression is as follows:

Au=(R1+R2)/RG+1=49.4kΩ / RG+1, where RG is in kΩ.

Figure 1 AD620 amplifier circuit [page]

2.2 Calculation of Band-stop Network

Stopband network circuit (see the competition question for details). According to Kirchhoff's law:

I1=I2+I3 (1)

U1= I1Z1+I3Z3 (2)

I3Z3= I2Z2+ U2 (3)

U2= I2RL=600*I2 (4)

From equations (1)(2)(3)(4), we can get the relationship between U1 and U2:

(Wherein, Z1, Z2 and Z3 are the total impedances of each resonant network respectively)

The amplitude-frequency characteristics of the output signal of the band-stop network measured by the Signal Analyzer in the Tina simulation software are shown in Figure 2.

Figure 2 Amplitude-frequency characteristics of the output signal of the band-stop network [page]

2.3 Digital signal equalization processing module circuit design

The essence of equalization technology is to complete the optimal filtering of random signals under certain optimization rules. Therefore, the problem of amplitude-frequency equalization of the signal is transformed into a filter design problem. In most communication systems using equalizers, the channel characteristics are unknown; and in many cases, the channel response is time-varying. In this case, the equalizer should be designed to be adjustable to the channel response; for time-varying channels, it should be designed to be adaptive to the time variation of the channel response. Therefore, adaptive equalizers are widely used in communication systems. However, in this competition, because it uses a band-stop network to simulate the actual channel, but all device parameters in the band-stop network are fixed values, there is no time-varying problem, so the designed filter coefficients do not need to be adaptive.

The equalization module uses Altera's CycloneII series FPGA as the core of signal filtering processing; the A/D conversion module uses TI's high-speed 8-bit A/D converter TLC5540, whose maximum conversion rate can reach 40 megabytes per second; the D/A module uses the 10-bit high-speed conversion chip THS5651.

In order to compensate for the attenuation shown in Figure 2, the equalization module uses the superposition of a low-pass filter and a high-pass filter with a cutoff frequency of 400HZ. The principle diagram of the filter group is shown in Figure 3.

2.4 Power Amplifier Circuit Design

According to the requirements of the topic, the final power amplifier circuit is implemented with discrete high-power MOS tubes. Compared with discrete OCL low-power amplifiers, MOS tube amplifiers have the advantages of small excitation power, large output power, negative temperature coefficient of output drain current, safety and reliability, high operating frequency, and simple biasing. The circuit is shown in Figure 3. The output of the op amp is used as the input of the OCL to achieve the effect of suppressing zero drift. In this scheme, a triode is used to drive the MOS tube, and the capacitors C4 and C5 between the collector and base are high-frequency vibration-proof capacitors. (Note: The data in the figure are reference values)

Figure 3 MOS tube power amplifier

The actual power is lower than this value, and the efficiency of the circuit is calculated by measurement. [page]

3 Software Design

Altera provides a digital filter design method based on Matlab and DSP Builder. Using DSP Builder, you can easily design FIR filters in a graphical environment, and the filter coefficients can be calculated by Matlab's filter design tool FDATool. This article uses direct I type to implement the FIR filter. First, design a 4th-order FIR filter section with variable coefficients. Then, by continuously calling the FIR filter section and cascading it, the high-order filter design is completed.

4 Experimental results and conclusions

Figure 4 singaltap test results

Figure 4 shows the test results obtained using the embedded logic analyzer SingalTap. Among them, XIN is the input signal obtained by A/D sampling, and YOUT is the output signal processed by the equalization program. From the output YOUT, it can be clearly observed that the program compensates for the input signal, removes noise, stabilizes the waveform, and plays a role in equalizing the signal. This design makes full use of the advantages of FPGA in digital signal processing, uses FPGA as a platform in the digital amplitude equalization module, and realizes high-speed processing of digital signal amplitude equalization. At the same time, the pre-amplifier circuit in this design can not only meet the various indicators in the competition question, but also realize the selectivity of gain, and can be used in other small signal amplification occasions.