Synchronous control scheme for high-power parallel UPS based on controller

1. Introduction

With the continuous development of information processing technology, especially the widespread application of computers and the rapid development of the Internet, modern information equipment has higher and higher requirements for the reliability of uninterruptible power supply (UPS) power supply systems. The reliability of uninterruptible power supply (UPS) has attracted more and more attention, and the uninterruptible power supply (UPS) parallel power supply system has gradually become the first; how to ensure the stable and reliable operation of the UPS parallel system under the harsh conditions of the power grid is a problem that UPS manufacturers need to consider. This article introduces a high-power parallel UPS synchronous control solution based on TI's TMS320C240 DSP controller. Synchronization with the power grid and synchronization between each UPS in the parallel system have become the key to the control of the parallel UPS system. The core part of the UPS parallel system is a highly accurate phase-locked loop. The analog phase-locked loop is a mature technology and has been widely used in many fields with its unique and excellent performance. However, with the development of digital technology, the full digital control of UPS is the general trend. Therefore, the phase-locked loop has gradually transitioned to digitalization. The digital DSP control phase-locked loop is more convenient to implement than the analog phase-locked loop. At the same time, it uses software instead of hardware to implement it. It can also be combined with other functions of the system for unified design and cost saving.

2. TMS320C240 DSP controller introduction

TMS320C240 is a 16-bit fixed-point DSP specially developed by TI for digital motor control applications. It provides an ideal solution for control system applications. It has the following main features: 3 general-purpose timers that can output 3 comparison/PWM pulses; 3 full comparison units that can output 3 pairs of comparison/PWM pulses with dead-zone control; 3 single comparison units that can output 3 comparison/PWM pulses; 4 capture pins CAP for high-speed I/O management; two groups of 8-channel 10-bit 10-microsecond A/D converters; watchdog timer and timer interrupt timer; on-chip ROM or Flash memory, etc.

3. Synchronous control scheme of parallel system UPS

1) UPS phase-lock control principle

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2) Implementation of synchronous phase lock of parallel UPS system

When the parallel system UPS switches between the mains and the inverter, if the output waveforms of the two are inconsistent at the moment of switching, it will cause power interruption. On the other hand, it may also damage the UPS due to excessive circulating current between the two voltage sources. In order to ensure that there is no circulating current when switching between the mains and the inverter of the UPS system, it is necessary to ensure that the mains waveform and the inverter waveform are close in phase; therefore, a device is needed to detect the phase change of the mains and to control the phase and frequency of the inverter output voltage so that the inverter and the mains can run synchronously.

For the phase locking of the parallel system UPS, a two-stage phase-locked structure can be used. The first-stage phase-locked loop is also called external synchronization, which means that each UPS in the parallel system tracks the phase and frequency of the mains and performs phase synchronization control with each other, that is, the synchronization of the UPS and the bypass mains is realized. The second-stage phase-locked loop is also called internal synchronization, which refers to the frequency and phase tracking and synchronization control based on the output voltage of each UPS, which realizes the synchronization between each UPS. Both stages of the phase-locked loop use PI regulators, among which the internal synchronization speed is faster and the accuracy is very high (within ±10μs), which ensures that the parallel circulation between UPS can be minimized. The external synchronization PI regulator is slower, which ensures smooth switching between the bypass and the inverter. Each stage of the phase-locked loop includes phase error detection and regulator adjustment. The following describes how each stage of the phase-locked loop is implemented.

The phase-locked block diagram in the parallel system is:

External synchronization: The input of the two UPS, i.e. the mains, is shaped into a square wave by the comparator circuit. After being integrated by the synchronous bus, the square wave signal is sent to the capture unit CAP1 pin of the DSP of each UPS. The rising edge or falling edge capture is set. When the square wave signal jumps accordingly, it enters the capture 1 interrupt to read the value of the counter T2CNT as the feedback signal of the PI regulator. The phase difference can be obtained by comparing it with the set value, and then the adjustment amount is formed through the calculation of the PI regulator, which is used to change the value of T2PR, so that the inverter output tracks the mains reference.

Internal synchronization: T2 counter is used as the phase and frequency reference of UPS sinusoidal output. To ensure synchronization among all UPS, all UPS use T2CNT to generate a square wave. After being integrated by the synchronous bus, the square wave is sent to the CAP2 port of all UPS. When the square wave signal jumps accordingly, it enters the capture 2 interrupt to clear T2CNT, ensuring that the internal synchronization setting is synchronized.

The T2CNT value is read as the feedback value in the interrupt corresponding to the midpoint of the sine wave, compared with T2PR/2, and then the adjustment value obtained after the PI regulator operation is used to change the value of T1PR, so that the inverter output sine wave and T2 counter are synchronized, so that the inverter output remains synchronized.

The software algorithm of phase locking is shown in Figure 1 and Figure 2:

Figure 1[page]

Figure 2

Its DSP synchronization algorithm is shown in Figure 3 below:

Figure 3[page]

4. Experimental results:

1) Synchronous phase locking between UPS and mains grid: Figure 4 below shows the synchronous phase locking between the UPS inverter output waveform and the mains waveform when the UPS is in mains power state. The phase locking accuracy can be guaranteed to be within 20 microseconds through DSP control.

Figure 4

2) Synchronous phase locking between UPS and generator: The figure below shows the synchronous phase locking between the inverter output and the generator waveform when the UPS is powered by a generator. The figure below shows that the use of the above-mentioned synchronous control algorithm can well ensure the matching between the UPS and the generator.

Figure 5

4. Conclusion

The two-level phase lock achieved by DSP can effectively solve the problem of synchronous control between the parallel system UPS and the mains, and between each UPS. A large number of experiments have shown that this phase lock control method can achieve good synchronization accuracy. No matter how the mains power changes, from abnormal to normal, from normal to abnormal, and the frequency changes suddenly within the range, the phase difference between the inverter output waveforms of each UPS is less than 50us, which is fully prepared for better current sharing between the parallel system UPS.