High-speed AD conversion based on FPGA

Abstract: In radar design, the received signal needs to be converted to digital first. The conversion speed and accuracy directly determine the accuracy of subsequent FFT operations, which ultimately affects the radar measurement accuracy. This paper introduces a fast 14-bit serial AD conversion based on FPGA using the chip ADS7890, and explains the software and hardware of the system. The hardware part mainly includes the basic peripheral circuit of ADS7890 and the control connection between the chip EP2C35F672C and it. The software part is programmed using Quartus II 8.0.
Keywords: FPGA; radar; AD conversion; ADS7890

. Current real-time ranging technologies include ultrasonic ranging, laser ranging, radar ranging, etc. In principle, the above ranging methods are similar, but millimeter-wave radar ranging overcomes some shortcomings of other detection methods in use. Millimeter-wave radar has stable detection performance. Compared with optics, it is not easily affected by the surface shape and color of the object. Compared with ultrasound and infrared, it is not affected by atmospheric turbulence and is less affected by rain, fog, snow, sunlight, dust, etc. The signal received by the radar is a frequency modulated continuous wave signal. With the development of digitalization, more and more analog signals need to be converted into digital signals for processing in the fields of detection and control. AD conversion is the process of outputting the input analog signal in binary digital form. According to Shannon's theorem: if the highest frequency of the analog signal that changes with time is ω, as long as the sampling frequency ωs≥2ωmax is used, the sample series (f1*(t), f2*(t), ...) taken out is sufficient to represent (or restore) f(t). It mainly includes four processes: sampling, holding, quantization and programming.
Corresponding to specific applications, AD conversion requirements are different. In the design of high-frequency radar, AD conversion is required to have a higher conversion speed in order to measure the distance in real time; and the final radar ranging accuracy is directly related to the number of bits of AD conversion and FFT. Some microcontrollers with built-in AD not only have slow data processing speed, but also the number of AD bits does not meet the requirements. Therefore, this design adopts an FPGA-based platform and uses ADS7890 to achieve fast and high-precision analog-to-digital conversion.

1 System hardware circuit
The main overall structure of the system is shown in Figure 1.

The system uses the chip EP2C35F672C6 of ALTERA as the control core to control ADS7890 and process the conversion result data. Radar IVS-167 can be used for radar ranging, which is a K-band radar transceiver with VCO in the IVS (Innosent VCO stereo) series launched by Innosent. Due to the use of a planar microstrip antenna structure and the integration of the transmitting and receiving antennas, its appearance is very small. It is not only energy-saving and power-saving at work, but also very easy to integrate into various circuits and easy to build module protection facilities in the installation environment.
In this design, the radar receiving signal is used as the analog signal input, and the input signal is made to meet the requirements of the AD conversion chip through the power amplifier circuit, and then the FPGA is used to generate the timing control ADS7890 to start and end the serial transmission of the digital signal, and the received data is processed and the result is displayed through the LED.
1.1 Chip ADS7890
ADS7890 is a high-speed AD conversion chip, including an analog 14-bit serial AD converter with an internal reference voltage of 2.5 V. Its maximum sampling rate is 1.25 MSPS. It has 48 pins and can be used as an SPI or DSP interface. The chip contains a power saving device and enters a power saving mode when the conversion speed is low. The chip can be used in photoelectric sensors, motor current/voltage sensors, medical testing instruments, high-speed data acquisition systems, etc. [page]

The basic peripheral circuit of ADS7890 is shown in Figure 2. The analog ground and digital ground are separated. The 5 pins SDO and SDO are connected to the control chip.

1.2 Introduction to FPGA
FPGA (field programmable gate array) is a programmable logic device developed on the basis of PAL and other logic devices. It is relatively large in scale and can replace hundreds of general-purpose IC chips. Its structure mainly consists of three parts: a two-dimensional array of logic blocks, which constitutes its logic component core; input/output blocks; and interconnection resources connecting logic blocks. With the continuous improvement of ultra-large-scale integrated circuit technology, the scale of FPGA is getting larger and larger. Its single-chip logic gate count has reached millions of gates, and its functions are constantly enhanced. Users can complete the design simply and quickly based on it. This design uses the chip EP2C35F672C6.
The main features of using FPGA to design digital system circuits are as follows:
1) Flexible design FPGA is set by the program stored in the on-chip RAM to set its working state. Therefore, the on-chip RAM needs to be programmed when working. Users can use different programming methods according to different configuration modes.
2) High integration A piece of FPGA can replace several, dozens or even hundreds of small and medium-sized digital integrated circuit chips.
3) Fast working speed The design concept of FPGA is parallel design concept, rather than sequential execution software concept, so the design greatly improves the working speed of the system.
4) Reduce costs With the development of FPGA technology, FPGA has overcome its own high price disadvantages and has a high cost performance.

2 System software design
The basic control timing diagram of FPGA is shown in Figure 3. The FS bit is for data frame format adjustment. When it is high, it is SPI mode, and when it is low, it is DSP mode. This design is used for SPI, and FS is set high. The falling edge of CS triggers ADS7890 to send data, and sends one bit of data on the rising edge of SCLK. 14 pulses correspond to the 14-bit result of AD conversion. After that, 1 or 2 SCLK cycles are used as delay to ensure the correctness of the AD result. Set a BUSY bit as a busy flag, and do not accept data after setting it high. Set a reset bit RESRT. SDO is the data transmission bit.

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The programming design uses VHDL language. VHDL is mainly used to describe the structure, behavior, function and interface of digital systems. In addition to the statements containing many hardware features, the language form and description style and syntax of VHDL are very similar to general computer high-level languages. A complete VHDL language program usually contains 5 parts: entity, structure, configuration, package and library.
The structure definition in the source program is as follows. Note that the input of ADS7890 corresponds to the output of EP2C35F672C6.
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3 Conclusion
With the development of digitalization, AD conversion has been fully applied in various fields, and the requirements for it are getting higher and higher. This design uses a highly integrated FPGA as the hardware platform to realize the control application of the high-resolution analog-to-digital conversion chip ADS7890. It has high conversion accuracy and is sensitive to fast-changing input signals. The system test is accurate, stable and reliable.