Design of PLL Frequency Synthesizer Based on FPGA

Frequency synthesis technology is an important part of modern communication. It converts a high-stability and high-accuracy reference frequency into an arbitrary frequency with the same stability and accuracy through arithmetic operations. The frequency synthesizer is the heart of the electronic system and one of the key factors affecting the performance of the electronic system. This paper combines FPGA technology, phase-locked loop technology, and frequency synthesis technology to design an integer/half-integer frequency synthesizer, which can be easily applied to phase-locked loop teaching and has certain practical value.  

1 Basic principles of PLL frequency synthesizer  

Frequency synthesizers are mainly divided into four types: direct, phase-locked, direct digital, and hybrid. At present, phase-locked and digital types are easy to realize serialization, miniaturization, modularization, and engineering, and their performance is getting better and better. They have gradually become the most typical and widely used frequency synthesizers [1]. This paper mainly adopts the integrated phase-locked loop PLL phase-Lockde Loop chip CD4046 and uses FPGA to realize PLL frequency synthesizer.  

Phase-locked frequency synthesizer is composed of PLL. The principle block diagram of a typical phase-locked frequency synthesizer is shown in Figure 1.  



  


Its working process can be simply described as follows: the average DC value of the phase detector output current multiplied by the impedance of the loop filter forms the input control voltage of the VCO. The VCO is a voltage-frequency conversion device with a proportional constant. The control voltage of the loop filter adjusts the output phase of the VCO, and after dividing by N, it is equal to the phase of the comparison frequency. Because the phase is the integral of the frequency, this process also applies to the frequency. The output frequency can be expressed as:  



  


Formula 1 is only valid when the PLL is in the locked state, and it is not valid in the intermediate process of the PLL being readjusted to the locked state. In actual applications, the R value is fixed, the N value is variable [2], and XTAL is the frequency of the input signal.  

2 System Design  

The functions of the entire system are mainly implemented by the FPGA chip EPF10K10 LC84-4 to control related hardware. The principle block diagram of this system is shown in Figure 2.  



  


As can be seen from Figure 2, on the one hand, the 40 MHz active crystal oscillator is divided by the control of the FPGA to obtain a 1 kHz frequency signal, which is used as the input reference frequency division of the CD4046. The output signal of the VCO of the CD4046 is directly input into the integer frequency division module and the half-integer frequency division module; on the other hand, the keyboard scans and outputs the key value, which is sent to the functional module. If the functional module indicates "OK", the key value is sent as the frequency division coefficient to the integer frequency division module and the half-integer frequency division module to divide the signal input by the VCO respectively; if the functional module indicates "clear", the frequency division coefficient is cleared. The last bit of the key value directly controls the two-way selection module: if the last bit of the key value is "0", the two-way selection module is controlled to output the integer module result; if the last bit of the key value is "5", the two-way selection module is controlled to output the half-integer module result. The result of the frequency division output is compared with the reference frequency of the phase-locked loop in the phase detector, and a Ud voltage signal corresponding to the phase difference of the two signals is generated. The high-frequency components and noise in Ud are filtered out by the loop filter, and Uc is output. Uc is then input into the VCO, so that the oscillation frequency of the voltage-controlled oscillator keeps approaching the frequency of the input signal, and finally the loop is locked, and the VCO outputs a stable frequency.  

During the operation, the FPGA controls the change of the preset N/N+0.5. When N/N+0.5 changes, the output signal frequency response changes with the input signal. At the same time, the FPGA also realizes the functions of keyboard scanning and LCD display.  

2.1 System hardware design  

The hardware is shown in Figure 3. The system part is mainly composed of 7 parts: external system clock, 4×4 keyboard control circuit, FPGA processing chip, EPC2LC20 EPROM chip, PLL chip CD4046 and its peripheral circuit, LCD 1602 display module, oscilloscope. This design uses the FPGA dedicated configuration chip EPC2, and downloads the program to the FPGA chip multiple times through the download cable ByteBlaster MV. The system uses FPGA chip as the control center, inputs control information by key scanning, and displays it on the LCD screen. It can conveniently and intuitively demonstrate the application of PLL chip CD4046 in frequency synthesis technology, and achieve the expected index requirements. The specific models of the main hardware in this design are: LCD TC1602A-01T, FPGA chip EPF10K10LC84-4, 40.000 MHz active crystal oscillator HO-12B.  



  


2.2 System software design  

By writing VHDL program to realize integer/half-integer frequency division, and using Quartus II and ModelSim, the author completed the design and simulation of VHDL program.  

The functional block diagram of the system software is shown in Figure 4. [page]



  


The specific working process of the system is as follows:  

The keyboard scanning module is responsible for scanning the keys, outputting the key values, and the key values ​​are input into the 1602 LCD module for display. At the same time, the key values ​​are input into the frequency division module in the FPGA through the function key module. When the function module is "OK", the key values ​​are input into the FPGA frequency division module, and the frequency division coefficient N is equal to the input key value. When the function module is "cleared", the frequency division coefficient N in the FPGA frequency division module will be cleared.  

3 System test and results  

Test instrument: INSTEK GOS-620 (20 MHz analog oscilloscope)  

Test temperature: room temperature  

3.1 Check whether the system is locked  

When the keyboard input is from 1 to 999.5, the waveform of the No. 1 pin of the CD4046 is shown in Figure 5, indicating that the PLL is in the locked state.  



  


3.2 Detection of lower frequency integer/half-integer frequency division  

When N=3, 9, 13, 1.5, 5.5, 9.5, and the input frequency is 1 kHz, the output waveform of CD4046 is shown in Figure 6 (a), (b), (c), (e), (f), (g) respectively. It can be clearly read from the figure that the output is 3 kHz, 9 kHz, 13 kHz, 1.5 kHz, 5.5 kHz and 9.5 kHz respectively. This is consistent with the results predicted in theory.  



  


3.3 Detection of higher frequency integer/half-integer division  

When N is a higher value, it is difficult to directly see by comparing the input and output waveforms of CD4046. At this time, the input still uses a frequency value of 1kHz, and the output frequency value is directly viewed. The waveforms when N=100, 500, 999, and 999.5 are shown in Figures 7(a), (b), (c), and (d) respectively.  



  


From Figure 7(a), we can see that the measured frequency is 1/(10×10-6) Hz=100 kHz.  

From Figure 7(b), we can see that the measured frequency is 2/(10×10-6) Hz=500 kHz.  

From Figure 7(c),   we can

see that the measured frequency is approximately 1/(10×10-6) Hz=1 MHz. From Figure 7(d),  

we can see that the measured value is consistent with the theoretically predicted result.  

3.4 Error Analysis  

The reason why the duty cycle of the waveform at a lower frequency is not the standard 50% is that the feedback signal generated after the CD4046 output frequency passes through the FPGA frequency division module is only a pulse signal. This pulse signal needs to be compared with the 1kHz standard signal entering and exiting the CD4046 for phase comparison, and the duty cycle of the standard signal is 50%. This results in the signal waveform generated after the phase comparison having a duty cycle of not 50%. The analog oscilloscope used in the system test is not very good for displaying low-frequency duty cycles other than 50%. This is most likely the main reason why the waveform is not very standard.  

After the test was completed, a digital oscilloscope was used to specifically detect the output frequency of CD4046, and the result was almost consistent with the theoretical calculation.  

This system combines FPGA technology, phase-locked loop technology, and frequency synthesis technology to design an integer/half-integer frequency synthesizer with an output range of 1 kHz to 999.5 kHz and a step frequency of 0.5 kHz. Compared with previous experimental devices, the system has improved performance indicators and intuitiveness. It can not only be used for teaching experiments, but also as a frequency source and frequency meter.