How to suppress IGBT collector overvoltage spike
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When the IGBT is turned off, the collector current Ic decreases rapidly to 0, and the rapidly changing di/dt flows through the system stray inductance, generating an induced voltage ΔV. ΔV is superimposed on the bus voltage, causing the IGBT to be subjected to higher-than-usual voltage stress. Even if this voltage spike is short-lived, it may cause permanent damage to the IGBT.
di/dt is related to the characteristics of the IGBT chip and the device current when it is turned off. When the device is turned off in a short circuit or overcurrent state, the collector voltage overshoot will be extremely large and may exceed the rated value, thereby damaging the IGBT.
Therefore, how to suppress the voltage spike during shutdown is a topic worth discussing.
Calculation formula from collector overshoot voltage:
V=Ls*di/dt
We can see that there are two ways to reduce voltage overshoot:
1. Reduce system stray inductance
2. Reduce the current, thereby reducing the current change rate di/dt
3. Drive slower to reduce the current change rate di/dt
Reducing system noise is a system-level issue, which we will discuss in a separate topic.
However, reducing the current change rate di/dt will increase the turn-off loss. How to resolve this contradiction?
This article mainly wants to explore some methods to reduce the current change rate and thus suppress voltage overshoot from the perspective of drive design.
To reduce the current change rate, the first method that many people think of is to increase the gate resistance, but this method is not always useful, especially for FS+trench stop technology. Slightly increasing the gate resistance may even increase di/dt. Only when the gate resistance increases to a very large value can di/dt be reduced. Increasing the gate turn-off resistance blindly will significantly increase the turn-off loss, so this method is not advisable.
The turn-off waveform of IGBT4 changes the gate resistance, but the collector overvoltage does not change significantly.
So besides increasing the gate resistance, is there any other way to reduce di/dt? From a driver perspective, there are three ways:
1 Two-level shutdown
The idea of two-level shutdown is to slow down the shutdown speed and reduce di/dt during the shutdown process, thereby reducing the shutdown overvoltage to a reasonable value. When the IGBT is turned off, the gate voltage is not directly reduced to 0V or a negative voltage, but in a very short time, the gate voltage first drops to UTLTO, which is lower than the normal conduction voltage, but higher than the voltage of the Miller platform. Then it is reduced from UTLTO to 0V or a negative voltage. Generally speaking, UTLTO can choose a voltage between 9 and 14V, and the voltage and duration of UTLTO are adjustable.
The two-level shutdown function can be integrated into the IGBT driver chip, such as 1ED020I12-FT. The voltage and duration of the two-level shutdown are usually implemented with a capacitor CTLTO or a combination of a capacitor and a resistor. When the capacitor is charged to a specific value, the output signal UOUT of the driver is triggered. If the input signal Uin is shorter than the set tTLTO, the input signal is usually suppressed, and the output signal remains unchanged.
The following figure shows the turn-off short-circuit current comparison with and without the TLTO function. Figure a shows the short-circuit turned off without TLTO technology, while Figure b shows the waveform with TLTO turned off. It can be clearly seen that the strong oscillations in the gate voltage and emitter-collector voltage are significantly reduced and, more importantly, the generated overvoltage is reduced. In this example, a peak voltage of 1125V appears in Figure a. In the measurement method shown in Figure b, the voltage is only 733V (in each case the DC bus voltage is 400V and a 400A/1.2kV IGBT is used).
(a) No TLTO function
(b) With TLTO function
The two-level shutdown function can be integrated into the driver chip. The traditional IGBT driver IC with integrated two-level shutdown function is shown in the figure below. The TLSET pin is connected to a Schottky diode and a capacitor. The Schottky diode is used to set the voltage of the two-level shutdown; and the capacitor is used to set the time of the two-level shutdown.
1ED020I12_BT/FT
Infineon's latest X3 Enhanced driver chip, 1ED38X1MX12M, does not require external capacitors and resistors. The level and duration of the two-level shutdown can be set through digital configuration, which can simplify circuit design and BOM.
1ED38X1MX12M
1ED38X1MX12M two-level shutdown timing diagram
1ED38X1MX12M two-level judgment parameter setting gear
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