Dual-channel rotary transformer angle measurement system based on FPGA

Rotary transformer is an electromagnetic induction sensor used to measure the angular displacement and angular velocity of the rotating shaft of a rotating object. It consists of a stator and a rotor. The stator winding serves as the primary side of the transformer and receives the excitation voltage. The rotor winding serves as the secondary side of the transformer and obtains the induced voltage through electromagnetic coupling. In order to improve the measurement accuracy, a dual-channel rotary transformer is used . The dual-channel rotary transformer uses single-phase stator excitation and two-phase stator induction output. After the excitation voltage Uref is added to the excitation winding, the sine and cosine voltages Uc_sin and Uc_cos are induced in the stator winding of the coarse shaft, and the sine and cosine voltages Uf_sin and Uf_cos are also induced in the stator winding of the fine shaft.

AD2S82A and AD2S80A are resolver- digital converters (RDCs) produced by Analog Devices Inc. of the United States . The AD2S8X series RDC can convert the rotation angle into a digital quantity proportional to the rotation angle. It is essentially a special analog-to-digital converter .

AD2S82A and AD2S80A are both products in the AD2S8X series. They are monolithic, variable-resolution RDCs. They use BiMOS technology and bipolar high-precision linear circuits in the manufacturing process, so they have the characteristics of high precision, stable performance and high reliability.

FPGA is the fourth generation of programmable logic devices (PLDs), with independent I/O interfaces and logic units CLB. It is flexible to use and highly applicable, especially for the design of complex logic. FPGA chips are one of the best choices for improving system integration and reliability.

1 Overall design plan

The overall block diagram of the system is shown in Figure 1. The integrated chips AD2S82A and AD2S80A are used as decoders for the output signals of the coarse and fine encoders of the resolver , respectively, to convert the analog output of the resolver into the corresponding digital quantity. They are then sent to the FPGA for error compensation and data combination, and the binary angle value after error compensation is converted into an angle value displayed in degrees, minutes and seconds in the FPGA through a segmented table lookup.

2 Hardware Circuit Design

2.1 Hardware circuit diagram

The hardware circuit block diagram is shown in Figure 2. The FPGA chip serves as the design core of the system and controls other circuit modules. At the same time, error compensation, data combination, and angle conversion are implemented in the FPGA.

2.2 Driver and A/D conversion module

The driving circuit mainly uses the integrated chip MAX038CPP to generate a sine wave. Since the sine wave current is very small, it cannot be used to directly drive the rotary transformer, and it needs to be power amplified. The power amplifier circuit mainly uses the integrated chip OPA541AM .

The sine wave generated by the drive circuit is used as the excitation signal of the dual-channel rotary transformer and added to its stator winding, so that sine waves and cosine waves are generated on its coarse channel rotor winding, which are sent to AD2S82A for decoding. At the same time, the sine waves and cosine waves generated by the fine channel rotor winding of the rotary transformer are sent to AD2S80A for decoding.

Through the chip select ports of AD2S82A and AD2S80A, their respective resolutions of 10 b, 12 b, 14 b, and 16 b can be selected, and the corresponding maximum tracking speeds are 1 040 r/s, 260 r/s, 65 r/s, and 16 125 r/s. Since they convert the resolver-type signal into natural binary code, a ratio tracking method is adopted, and the output digital angle is only related to the ratio of the input sine and cosine signals, but not to the absolute value, so it has a high noise suppression ability and can reduce the error caused by the long-distance transmission of the resolver. Here, both AD2S82A and AD2S-SOA select 12-bit output.

When AD2S82A and AD2S80A are in the process of operation, a busy signal will be generated at their respective BUSY ports. Use FPGA to detect these two busy signals. When one of the two chips is in the process of operation, FPGA sends a prohibition signal to the INHIBIT port of AD2S82A and AD2S80A to prohibit reading the conversion data of the two chips at this time. In this way, the two chips can work synchronously and prevent misreading of conversion results.

2.3 FPGA error compensation and data combination module

When the pole ratio of the coarse code disk and the fine code disk of the dual-channel rotary transformer is 1:32, the rotary transformer rotates 1 circle, and the coarse axis is equivalent to 1 circle, while the fine axis is equivalent to 32 circles. That is, the coarse axis rotates 1 circle, which is equivalent to 360°, while the fine axis rotates 1 circle, which is only 11.25° (360°/32). Therefore, the highest bit Q1 of the digital angle after fine axis decoding represents 5.625° (11.25°/2), which is equivalent to the P6 bit of the coarse axis. The weights of each bit of the coarse axis and fine axis after decoding are shown in Table 1.

Since the last few digits of the coarse axis are certainly not as accurate as those of the fine axis after being magnified 32 times, the principle of the coarse and fine digital angle combination is that both the coarse and fine axes output 12-digit digital angles, but the coarse axis only takes the upper 5 digits (P1~P5), while the fine axis takes the full 12 digits (Q1~Q12).

When the resolver rotates, there are various errors between the coarse code disk and the fine code disk, and the corresponding bits of the coarse and fine channels may change at different times. That is, after the coarse channel data changes, the data of the corresponding bits of the fine channel has not changed, and similarly, the fine channel data changes, while the data of the corresponding bits of the coarse channel has not changed. Therefore, error compensation must be performed on the decoded data.

It can be seen from Table 1 that the bits corresponding to the coarse channel and the fine channel are only P6 and Q1, both of which represent 5°37'30". When P6 and Q1 change asynchronously, error compensation is required. The error compensation module is written in VHDL language and implemented in FPGA. The program flow chart is shown in Figure 3.

2.4 Angle value conversion module

The angle value after error compensation is displayed in binary, that is, R1~R17 as shown in Table 1. Different bits represent different angle values. In order to facilitate display and subsequent circuit operations, the binary angle value must be converted to an angle value displayed in degrees, minutes and seconds. Direct conversion according to the weight of each bit involves multiple multiplication and division operations, which affects the speed of the entire circuit. Multiplication and division operations can be avoided by looking up the table, but direct table lookup requires a large ROM space. Here, the segmented table lookup method is used to divide the error-compensated data into integer degree bits R1~R3 ​​and minute and second bits R4~R17. R4~R17 are looked up in the table according to degrees, minutes and seconds, and then the integer degrees found and the integer degrees found by R1~R3 ​​are added. In this way, the ROM space can be reduced to about 1/8 of the original.

3 Simulation Verification

Now the three modules of error compensation, data combination and angle conversion are simulated. The simulation is based on the EP2C35F484C6 FGPA of Altera Company . Three test platforms are established in the simulation. The simulation results are shown in Figure 4.

The simulation clock cycle is 10 nS, dbl~dbl8 are the input signals of FPGA, where dbl is the highest bit. The high 6 bits of db dbl~db6 are the outputs of AD2S82A (P1~P6), the other bits of db db7~dbl8 are the outputs of AD2S80A (Ql~Q12), db_outl~db_out17 are the data after error compensation, and db_outl~db_outl7 are used to look up the table in segments. In Figure 4, deg is the degree output, min is the fraction output, and sec is the second output.

From the simulation results, it can be seen that when db6 (P5) and db7 (Q1) are different, error compensation is required. The data after error compensation can be used to obtain the correct angle value displayed in degrees, minutes and seconds through a segmented table lookup.

4 Conclusion

A dual-channel rotary transformer angle measurement system based on FPGA is proposed and established. The main feature of this solution is that it makes full use of the rich hardware resources of FPGA and implements complex mathematical operations and control operations with hardware, which greatly improves the conversion rate and the stability of the entire system. This solution can also be easily transplanted to rotary transformers or inductive synchronizers with more pole pairs , which can further improve the conversion accuracy.