Calculating Histogram in FPGA with One Clock

Histograms are often a useful tool for analyzing digital data. However, to obtain reliable results from a histogram, a large amount of data must be obtained, usually 100,000 to 1 million points. If you need to analyze the digital output of an ADC, you can use an FPGA (Figure 1).

The figure shows the histogram, RAM, and pulse generator sections used to capture and display the histogram calculated based on 14-bit data. The RAM block is the built-in RAM of the FPGA, while the histogram block is the VHDL (High-Level Design Language) code used for the calculation. The 14-bit parallel data Device_ Data[13..0] from the ADC enters the histogram block and enters the Rd_Addr input of the RAM. The RAM provides data at its address location RAMDataOut[ 15..0]. This data is looped back to the histogram block, which is incremented by 1 and sent to a 16-bit data output terminal DataOut[15..0]. When the WREN (write enable) terminal is at logic level 1, the data is written to the address at pin Wr_Addr[13..0]. This method is the same as if the data comes from Device_Data[13..0].

RAM has a fixed delay from input to output. That is, when the input is Rd_Addr, the data appears at its output RAMDataOut after a fixed delay. This delay varies with different FPGAs. Pay attention to this delay so that there is a delay of two clocks to Device_Data and then calculate the histogram. The delay in RAM should be less than two clock cycles; otherwise, there may be data loss. This constraint limits the maximum frequency of Device_Clk.

Cntr_Value gives the number of input data used to calculate the histogram. The Pulse_Gen block generates a pulse into the input Rst_Cntr to reset the counter. At this point, the histogram part calculates the histogram again with the next set of input data from Cntr_Value. Cntr_Value is 15 bits, but it can be increased to get more histogram data.

The Sel_Data and Rst_RAM signals reset the data stored in the FPGA RAM. When the Rst_RAM pin is high, all bits of the DataOut pin of the histogram block are 0. When the Sel_Data input pin of the histogram block is high, the output of RAM_Wr_Addr is not Device_Data, but an internally generated ramp that rises from 0 to 16384. The histogram block does not perform calculations because doing so would reset the address of the RAM.

Figure 1. The histogram calculation circuit obtains data from a RAM block in an FPGA.

When the FPGA has completed the histogram calculation, the RAM can select Sel_Data to be logic high and keep Rst_RAM to be logic low to read the histogram data. The data in the RAM address exits the output pins sequentially and the data can be transmitted to a PC. Since all blocks operate with a single clock Device_Clk, this design is simple and helps meet the timing constraints. This design can be easily modified to obtain 16-bit or 12-bit data histograms.