Design of Linear Array CCD Driver Based on FPGA

Abstract: Charge coupled device (CCD), as a new type of photoelectric device, is widely used in non-contact measurement. CCD drive design is one of the key issues in CCD application. In order to overcome the shortcomings of the early CCD drive circuit, such as large size, long design cycle, and difficult debugging, a linear array CCD drive method with adjustable integration time and frequency using programmable logic device FPGA is introduced, and the drive circuit scheme is described in hardware using Verilog language. The designed timing is simulated by QuartusII. The simulation results show that the design method of the drive timing is feasible.
Keywords: linear array CCD; programmable logic device; integration time; frequency

Charge coupled device (CCD) is an emerging solid imaging device-image sensor. It has the advantages of small size, light weight, high resolution, low noise, self-scanning, fast working speed, high sensitivity, and good reliability. It is highly valued by people and is widely used in image sensing, scene recognition, non-contact non-destructive testing, document scanning and other fields. The key technology of its application system lies in the generation of CCD drive signal and the processing of output signal. In the past, the driving method often used mainly focused on hardware implementation, which was difficult to debug and had poor flexibility. Although the single-chip microcomputer driving method is flexible in programming, it has the defects of more resource waste and low frequency. Complex programmable logic device FPGA has the advantages of flexible programming, high integration, fast speed, large capacity, low power consumption, good reliability, etc., and saves space on PCB boards, has good portability and flexible use. Therefore, combined with the actual application needs, the CCD driving timing design based on complex programmable logic device FPGA is designed, the driving circuit scheme is described in hardware using Verilog language, and the designed timing is simulated by QpartusⅡ.

1 CCD image sensor TCD1251UD
The TCD1251UD chip is a high-sensitivity, low-dark-current, dual-channel two-phase linear array CCD image sensor with 2,700 effective pixels produced by Toshiba Corporation of Japan. Its center distance is 11μm, the optimal operating frequency is 1 MHz, and the total length of the photosensitive unit array is 29.7 mm. The sensor can be used for fax, image scanning and OCR. Its structure includes: MOS capacitor storage gate, transfer gate electrode SH, CCD analog shift register φ1 and φ2 signal output unit OS and compensation output unit DOS.

2 TCD1251UD driving timing requirements
The driving pulse waveform of TCD1251UD is shown in Figure 1, and the timing relationship between each signal is shown in Table 1.

When the SH pulse is at a high level, the φ1 pulse is also at a high level, and a deep potential well is formed under them. The deep potential well of SH enables the deep potential well under the φ1 electrode to communicate with the MOS capacitor storage potential well, so that the signal charge in the MOS capacitor storage gate is transferred to the potential well under the φ1 electrode. When the SH level changes from high to low, the shallow potential well formed by the SH low level isolates the potential well under the MOS capacitor storage gate from the potential well under the φ1 electrode. The potential well of the storage gate enters the light integration state, and the analog shift register drives the signal charge to shift to the left under the action of the φ1 and φ2 pulses. Finally, the signal outputs a dummy signal and 2,700 effective pixel signals through the OS terminal, and the compensation signal is output from the DOS terminal. Due to the structural arrangement, the OS terminal first outputs 13 dummy unit signals; then outputs 51 dark signals; finally, continuously outputs 2,700 effective pixel unit signals; then outputs 9 dark signals, 2 parity detection signals and empty drive without signal. The number of empty drives is arbitrary, but must be greater than 0, otherwise it will affect the output of the next line of signals. Since the device is a two-line odd and even transmission, there must be at least 1 388 φ1 pulses in one SH cycle, that is, TφSH>1 388Tφ1. The technical indicators of each pulse of the CCD are: φ1 and φ2 are driving pulses, φ1 and φ2 are opposite in phase, both are square waves with a frequency of 0.5~2 MHz and a duty cycle of 1:2. This article requires that the frequency can be adjusted. SH is a transfer pulse. It can be seen from Figure 1 that when SH is high, φ1 must be synchronized to a high level. When SH is low, φ1 will also become low. However, the φ1 pulse must rise earlier and fall later than the SH pulse. That is, during parallel transfer, the φ1 pulse has a wide high-level pulse that lasts longer than when SH is high. From the above analysis, it can be concluded that TφSH>1388Tφ1, RS is a reset pulse, a square wave with a duty cycle of 1:4, and a frequency of 1~4 MHz. At the same time, the frequency is also required to be adjustable.

3 Implementation of drive timing
3.1 FPGA implementation of drive
timing In order to generate the timing used in the system, a CCD sensor drive timing generator based on complex programmable logic device FPGA was designed, using Altera's QuartusⅡ software development system. QuartusⅡ software development system is a fully integrated programmable logic design environment, which supports three input methods: hardware description language (VHDL and Verilog HDL), state diagram and schematic diagram, and has compilation, logic synthesis, simulation and other functions. Compared with other input methods, the input method of hardware programming language (such as VHDL or VerilogHDL) has good portability and readability, so it becomes the first choice for this design. Among them, Verilog HDL has the advantages of flexible programming and easy use, which is accepted by many designs. The overall design idea is to divide the drive timing into three modules, namely AD0832, Divider and CCD_Driver. The data collected and output by the AD0832 module is processed by the Divider module and then input to the CCD_Driver module to adjust the integration time and driving frequency of the CCD. At the same time, the CCD_Driver module outputs 4 signals to drive the CCD. The overall design idea of ​​the CCD_Driver module is to use the adjustable clock in_clk and integration time INTER_TIME as inputs and they correspond to the outputs CCD_clk and Ctr_Time_Out[12. 0] of the Dirider module, and generate four signals SH, RS, PH1, and PH2 as outputs to directly drive the CCD. The driving frequency RS and integration time SH are adjustable. The design of the CCD drive timing is shown in Figure 2. The function implemented by the CCD_Driver module is to divide the clock input (in_clk) by two to obtain the Q1 and Q2 signals respectively, and divide it by four to obtain temp_ph. The signal temp_ph is used as the counting clock input, and the signals temp_sh1 and temp_sh2 are triggered at its rising and falling edges respectively. Q1, Q2, temp_ph, temp_sh1, temp_sh2 are combined with logic operations to obtain transfer pulse SH, reset pulse RS, clock signals PH1, PH2 respectively. The transfer pulse SH and reset pulse RS have adjustable frequencies. When using VerilogHDL to write a program, the phase of the clock PH2 is required to be opposite to that of the PH1 signal. Q1 is a two-frequency signal triggered at the rising edge of the clock in_clk, and Q2 is a two-frequency signal triggered at the falling edge of the clock in_clk. After inverting Q2, it is ANDed with Q1 to generate the RS signal. Since there is a certain periodic relationship between the SH, RS, PH1, and PH2 signals, the base signal temp_ph is obtained by triggering the flip of the two-frequency division at the falling edge of Q1. The signal temp_ph is used as the counting clock input, and is triggered at its rising and falling edges respectively, and the high and low level time of temp_sh1 and temp_sh2 is controlled according to the integral time count. The SH signal is obtained by ANDing temp_sh1 and temp_sh2; the PH1 signal is obtained by ORing temp_ph, temp_sh1 and temp_sh2. PH1 is inverted to get the PH2 signal.

3.2 Simulation results
The above modules were designed and input on the QuartusⅡ software development system. After compilation and verification, the simulation waveform is shown in Figure 3.

From the simulation results, it can be seen that the generated driving pulse is completely consistent with the driving timing required by the linear array CCD-CCD-TCD1251UD, and can meet the requirements of the CCD driving circuit.

4 Conclusion
The use of FPGA devices to implement the design of CCD drivers has well met the needs of CCD applications to develop towards high speed, miniaturization, and intelligence. In the design, it is first necessary to understand the requirements of CCD driving timing and use hardware description language for scientific programming, so as to effectively meet the design requirements. This article uses a design example to illustrate the method of using FPGA to design CCD drivers. After simulation testing, it is verified that the design meets the CCD driving requirements.