Design of PPM Modulation and Demodulation System Based on FPGA

0 Introduction

At present, atmospheric laser communication, wireless infrared communication and emerging ultraviolet communication technologies are developing rapidly and are a hot topic in modern communication technology research. In particular, the emerging ultraviolet communication technology works in the so-called ultraviolet "sun blind zone". The background noise of ultraviolet light in this band can be regarded as zero, which also makes ultraviolet communication have the advantages of low eavesdropping rate, low bit resolution, omnidirectional and high anti-interference ability. Most optical communication systems use systems designed as intensity modulation/direct detection (IM/DD). There are many modulation methods used in intensity modulation/direct detection optical communication systems. Pulse position modulation (PPM) is an orthogonal modulation method. Compared with traditional on-off keying (OOK) modulation, it has higher optical power utilization and frequency band utilization, and can further improve the anti-interference ability of the transmission channel. In addition, PPM reduces the requirement for the average power of optical radiation. Low radiation power is particularly important for extending the working life of the transmitting light source, which can effectively improve the service life of the whole system.

Starting from engineering application, this paper designs the PPM modulation and demodulation system according to the basic principles and mathematical models of PPM, and completes the system simulation on Quartus using Verilog HDL language.

1 Basic principles and mathematical models of PPM

According to the pulse form, pulse position modulation can be divided into three types: single pulse position modulation (L-PPM), differential pulse position modulation (L-DPPM) and multiple pulse position modulation (MulTI-PPM). Considering the bandwidth utilization, transmission rate and practical engineering application, L-PPM is selected as the specific way to implement PPM.

L-PPM maps an n-bit binary data group to a single pulse signal at a certain time slot in a time period consisting of 2n time slots. It is easy to know that the information bit transmitted by an L-bit PPM modulated signal is log2L. If the n-bit data group is written as m=(m1, m2, ..., mn), and the time slot position is recorded as l, then the coding mapping relationship of this single pulse position modulation can be written as the following mathematical relationship: l=m1+2m2+...+2n-1mn, n∈{0, 1, ..., n-1). According to this relationship, the schematic diagram of 16-PPM is obtained, as shown in Figure 1.

2 PPM modulation system design

From the above discussion, it is not difficult to find that the modulation process of PPM is essentially a counting process. The program needs to calculate the value in the parallel data and output a high pulse at the corresponding time slot position, and no pulse is output at other positions, so as to ensure the one-to-one mapping of the signal.

This article is based on Verilog HDL language design. Taking 16-PPM as an example, its design idea is: According to the PPM modulation principle shown in Figure 1, PPM modulation counts parallel input data, so the serial input data should be converted from serial to parallel before modulation. Because it is 16-PPM, the number of time slots in one frame should be 16, and 4-bit data is converted from serial to parallel each time, so the clock signal that triggers the serial/parallel conversion is the quarter frequency of the time slot clock. The converted 4-bit parallel data needs to be compared with the hexadecimal counter to determine the time slot position of the high pulse in this frame. This requires that the parallel data can be maintained for one frame time so that it can be compared with the count value generated by the counter, so the latch controls the output of parallel data. When the parallel data is equal to the output value of the counter, a high level "1" is output, otherwise a low level "0" is output, thus generating the required PPM signal. The specific process is shown in Figure 2.

3 PPM demodulation system design

This article has introduced the PPM modulation process in detail. The demodulation process of the PPM signal is essentially the reverse process of PPM modulation, so the detailed demodulation process is omitted here. However, a very critical clock synchronization problem needs to be solved in the PPM demodulation process, including bit synchronization and frame synchronization.

3.1 PPM bit synchronization

The effect and efficiency of establishing bit synchronization and frame synchronization are related to the success of the entire PPM demodulation process. Bit synchronization is the basis of frame synchronization. There are two methods to achieve bit synchronization: inserting pilot signal and direct method. The inserting pilot signal method is to insert the required bit timing pilot signal at the zero point of the baseband signal spectrum; the direct method is to extract the bit synchronization signal directly from the received digital signal without sending a pilot signal specifically at the transmitting end. It is found from the PPM modulation process that the PPM signal contains time slot clock information, that is, the bit synchronization signal, and the direct method is suitable. The method of directly extracting bit synchronization is divided into filtering method and phase-locked loop method. Now, digital phase-locked loop is usually used to extract bit synchronization signal. Digital phase-locked loop solves the shortcomings of analog phase-locked loop such as DC zero drift, device saturation, and susceptibility to power supply and ambient temperature changes, and has the advantages of high reliability, small size, and easy integration. The literature has been elaborated in detail, and this article is limited in space and will not be repeated here.

3.2 PPM frame synchronization

Frame synchronization can be achieved by using the insertion method or the direct method. The insertion method is to insert a special code element at the head of each frame to identify the starting position of each frame, such as inserting a Barker code. However, this will complicate the modulation and demodulation process of PPM, and the inserted code element occupies the time slot originally used to transmit information, which will reduce the transmission rate of the entire system. This paper uses the direct method to extract the frame synchronization signal.

Traditionally, frame synchronization for PPM demodulation is mostly achieved using a phase-locked loop (PLL)-based method. That is, a phase-locked loop is used to lock two "shoulder-to-shoulder" optical pulses. As shown in Figure 1, the two optical pulses between frame 3 and frame 4 are "shoulder-to-shoulder" optical pulses. Obviously, such optical pulses are relatively rare, especially as the modulation order increases, the probability of occurrence is bound to decrease, which seriously affects the speed of achieving frame synchronization. In addition, since the continuous "0" code of the PPM signal is too long, the phase-locked loop cannot be locked quickly and is easy to lose lock. Here, the characteristics of the PPM signal itself are used to extract the word synchronization clock using a digital logic circuit.

From the 16-PPM diagram, we can see that the PPM signal has three characteristics: First, each PPM frame consists of 16 time slots, but only one time slot is high level, and the rest are low levels; second, if 16 low levels appear consecutively, it means that these 16 low levels are definitely not in the same PPM frame, but in two adjacent frames; third, if 2 high levels appear consecutively, it means that these 2 high levels can only be in two adjacent frames.

Based on the above three characteristics of the PPM signal, the process of extracting the frame synchronization signal in FGPA is designed as follows: the received PPM modulated signal is input into the serial/parallel conversion unit. Under the control of the synchronous time slot clock, the serial PPM modulated signal is input in 16-bit parallel. This process is actually a 16-bit data shift process. Then the 16-bit data output in parallel is logically judged. If there is only one high level "1" in the 16-bit data, a high level is output, and a low level "0" is output in other cases. At the same time, the counter counts the time slot clock. The counter generates a carry high level "1" every 16 times, and the output is "0" at other times. The counter output is ANDed with the logic judgment output. If both are high level, the result of AND is "1", then a frame synchronization signal is output, otherwise no frame synchronization signal is output, but if the result of logic judgment is "0" and the counter output is "1", the low level output by the AND gate and the high level output by the counter need to be XORed to obtain a low level "0", and this low level is ANDed with the time slot clock that controls the counter, so that the counter pauses counting once, thereby gradually achieving frame synchronization by deducting the time slot clock. The specific design process is shown in Figure 3.

4 System Simulation

The whole system is simulated on the Quartus 8.0 platform. Figure 4 is the PPM modulation simulation diagram. ser_in is the serial input data, parr is the parallel data after serial/parallel conversion, and data_out is the output signal after PPM modulation. From the figure, we can see that the PPM modulation is correct. In order to better demonstrate the principle of gradual synchronization of the program, we choose to restore the frame synchronization from the 4-PPM signal, as shown in Figure 5. From the simulation, it is not difficult to see the gradual synchronization process of the frame synchronization output framclk_out.

Figure 6 is a PPM demodulation simulation diagram, and Figure 7 is a simulation of the entire system, that is, after the serial input data is modulated by PPM, the demodulation program extracts the frame synchronization from the modulated signal and demodulates the original serial input data. From Figure 7, we can see that there is a certain delay between the serial input data and the serial output data. On the one hand, this is because the hardware system itself has a delay, and the more important reason is that during PPM modulation, the comparator needs to wait for the first serial/parallel conversion to be completed before making a comparison and outputting a PPM signal, and the demodulation is performed based on the modulated PPM signal, which leads to a delay in the simulation, but this delay does not exist in actual application.

5 Conclusion

The FPGA-based PPM modulation and demodulation system was designed using the Verilog HDL language, and functional and timing simulations were performed on the modulation process, frame synchronization process, demodulation process, and the entire system on the Quartus 8 platform. From the simulation, it can be seen that the entire system has achieved the expected goal and can efficiently and stably complete the PPM modulation and demodulation process, laying the foundation for future practical application. However, on the other hand, it was also found in the simulation that the frame synchronization time was too long and needed further improvement.