FPGA-based channelized receiver

The electromagnetic environment of modern electronic battlefields is complex and changeable, and the signal environment is developing in the direction of density, complexity, and broadband occupation of electromagnetic spectrum. On the other hand, using array antennas to estimate the signal parameters of received signals is one of the conventional technical means in electronic reconnaissance systems. Therefore, broadband array receiving systems have broad application prospects. Traditional broadband array receivers use multiple single-channel receivers to work in parallel and receive signals at different frequencies in parallel to achieve the purpose of full frequency domain coverage. They can also be achieved by using multiple channels of multi-channel receivers to work in parallel and synchronously. The former increases the system cost and the complexity of making the entire parallel system work synchronously. The latter requires high signal processing complexity and feasibility of device implementation when the number of channels is relatively large and the index requirements are relatively high. Digital channelized array receivers based on polyphase filtering have shown high potential research and application value in the rapid search of frequency hopping signals in communication electronic warfare and the full probability interception of frequency-hopping radar signals in radar confrontation.

1 System composition

The system design is based on the channelization principle of multiphase filtering. The broadband array receiver is designed to process 3 analog signals with an intermediate frequency of 70 MHz and a bandwidth of 30 MHz on a single board at the same time. The sub-channel bandwidth is only 25 kHz, which is conducive to the refined signal sorting and processing of the back-end module. The channelization multiphase factor is 8. The out-of-band suppression is greater than 55 dB. The system can also upload the data of a certain sub-channel in the array to the PC through the PCI interface to display the channelization results. The system has a complete clock scheme, and when multiple boards are connected, the synchronization requirements of the array antenna can be met. In addition, since most of the digital signal processing of the system is completed in the FPGA, the entire system has the characteristics of low power consumption, small size, low cost and flexible operation. Figure 1 is a system block diagram of the channelized array receiver.

2 Hardware Circuit Design

The hardware design schematic diagram of the IF digital receiver is shown in Figure 2. The IF signal is input to the analog-to-digital converter in the form of a differential signal through a single-ended to differential circuit. AD*5 converts the analog signal into a digital signal and sends it to the FPGA for processing. The processing result of one chip is uploaded to the PC for display through PCI. The two clock distributors provide the multiple single-ended and differential clocks required by the system.

2.1 System Clock Design

The system clock is generated by a crystal oscillator or provided externally. This system uses a 102.4 MHz crystal oscillator. The crystal oscillator needs to provide clocks to both the FPGA and AD*5. In order to prevent its driving force from being insufficient, the design uses the high-speed clock distribution device CY2309 from CYPRESS . The clock input of AD*5 is in differential (LVPECL) form, and the frequency multiplication device ICS8735 can provide differential signals at the LVPECL level. Therefore, the 102.4 MHz clock output by the crystal oscillator is first divided into 5 paths through the clock distribution device CY2309, each of which is the same as the input. Three of them are directly provided to three FPGAs, one is connected to the clock output interface for use by the lower-level board, and one is converted into 3 differential clocks through the driver ICS8375 and provided to three AD*5s as sampling clocks. Since both CY 2309 and ICS8375 are zero-delay devices, this can keep the clocks synchronized between multiple boards and reduce the error caused by delay.

2.2 AD sampling circuit design

The analog-to-digital converter used in this system is AD*5 (14 bits), with a maximum sampling rate of 105 MS/s, an SNR of 73.5 dB at an intermediate frequency of 70 MHz, a SFDR of 89 dBc, and an analog bandwidth of up to 200 MHz.

The AD sampling rate is 102.4 MS/s. The sampling clock requires high quality and low phase noise. If the clock signal jitters greatly, the signal-to-noise ratio is easy to deteriorate, and it is difficult to ensure the accuracy of the effective sampling bit number. When wiring, the distance from the crystal oscillator to the clock input pin should be as short as possible and surrounded by ground to provide sufficient shortest return path. The sampling circuit is isolated from other digital circuits as much as possible. The partition-undivided solution is adopted in the design of analog-to-digital mixed circuits to improve the electromagnetic compatibility of the system. A large area of ​​copper should be applied to the ground under the entire sampling circuit to reduce possible electromagnetic interference, and also reduce interference to other circuits. In order to optimize performance, the clock signal is supplied in differential form, requiring AC coupling.

2.3 FPGA Part Design

The FPCA device uses the EP2S60 of Altera 's StratixⅡ series . StratixⅡ devices are manufactured based on 1.2V, 90nm advanced SRAM industry and have low power consumption. The EP2S60F672 has 48352 ALUTs, 40 equivalent LEs, 2544 192-bit RAM, 144 18x18 multipliers, and 12 PLLs .

The FPGA configuration device selected is EPC16 , and the synchronous parallel configuration method (FPP) is used to load the FPGA. The JTAG method can be used to load the program to the cascaded 3 FPGAs in sequence, and the program can also be loaded to the EPC-I6.

3 FPGA internal channelization module implementation

The channelization module based on polyphase filtering is the key point of this system. According to the literature, the polyphase filtering channelization structure is shown in Figure 3.

In Figure 3, the relationship between the branch signal xk(n) and the input signal x(n), as well as the branch filter Ek(n) and the prototype low-pass filter h0(n) is: xk(n)=x(nD-k), Ek(n)=h0(nD+k)k=0, 1, ..., D-1. Therefore, the data entering the branch and the branch filter coefficients are the delayed extraction of the input signal and the prototype low-pass filter coefficients. The length of the branch filter is defined as the polyphase factor, and the polyphase factor of this system is 8.

The prototype low-pass filter of the polyphase filter is generated by MATLAB, and the function REMEZ is used to optimize the FIR filter estimation algorithm. The filter designed here has a passband cutoff frequency of 12.5 kHz, a transition bandwidth of 11 kHz, a stopband attenuation of -100 dB, and an order of 16,383.

The efficient channelization structure based on the polyphase filter bank shown in Figure 3 has the following advantages: 1) Each branch shares a low-pass FIR filter, reducing the RAM resources used by the FPGA to store coefficients; 2) DFT can be implemented using the fast Fourier transform FFT, improving computational efficiency; 3) Due to the use of the polyphase filter structure, the amount of computation is greatly reduced and the feasibility is enhanced. These advantages provide a good way for the engineering implementation of the channelization structure.

4 Test Results

The system input test signal is a single-frequency sinusoidal signal with a VPP of 1 V. After the signal is sampled by AD, DDC, and channelized, the data results are uploaded to the PC via PCI for analysis and display.

In the interface made with Microsoft Visual C++6.0: the horizontal axis is the channel number, the vertical axis is the normalized power value (dB), and the contents displayed in data form include: the channel number corresponding to the maximum signal power, the dB value of the sub-channel output relative to the input amplitude, and the dB value of the two adjacent channels. As shown in Figures 4 and 5, the input signal frequencies are 70 MHz and 70.025 MHz respectively. After channelization, the spectrum lines can be output on the corresponding channel numbers, and the frequency resolution reaches 25 kHz. After repeated tests, the system's out-of-band suppression of adjacent channels has reached more than 55 dB.

5 Conclusion

The main components of the system include AD*5 and EP2S60, among which AD6* implements ADC, and EP2S60 is responsible for system control, communication, and algorithm implementation, and finally realizes the channelized receiving function. Therefore, the system has high flexibility and strong versatility, and can complete system structures with different index requirements and different modes through software reloading or upgrading. When multiple boards are connected, a larger array system can be formed, which can be used for D OA and DBF.