Domestic high-end automotive intelligent driving chips spark a war of words

On July 27, at the 2024 NIO Innovation Technology Day, NIO Chairman Li Bin announced that the world's first automotive-grade 5nm smart driving chip, Shenji NX9031, was successfully taped out , and both the chip and the underlying software were independently designed.

According to reports, this chip uses a 32-core CPU architecture, built-in LP DDR5 x, 8533Mbps RAM, has a pixel processing capacity of 6.5G Pixel/s, and a processing delay of less than 5ms. Li Bin said that the Shenji NX9031 has more than 50 billion transistors . Whether in terms of comprehensive capabilities or execution efficiency, a self-developed chip can achieve the performance of 4 industry flagship chips.

This time, Li Bin's speech caused some controversy in the semiconductor industry because he claimed that the Shenji NX9031 is the world's first automotive-grade 5nm smart driving chip. However, before that, there have been 5nm chips that can be used for smart driving systems, such as NXP 's S32N55 processor and Ambarella's CV3 series domain controller .

01. What is the point of dispute?

Li Bin said that Shenji NX9031 is the world's first 5nm smart driving chip, which is debatable. First, let's take a look at the 5nm automotive chips launched by NXP and Ambarella . It can be said that NXP is the first company in the industry to announce the use of 5nm process technology to produce automotive chips. As early as June 2020, the company announced this news, and the foundry partner is TSMC . The S32N55 processor using 5nm process integrates 16 Arm Cortex-R52 real-time processor cores and runs at a frequency of 1.2 GHz, which can meet the high computing power requirements of software-defined cars .

The S32N55's Cortex-R5 2 core can run in split or lock-step mode to support ASIL ISO 26262 functional safety levels. Two pairs of auxiliary lock-step Cortex-M7 cores support system and communication management. As the central vehicle controller solution for the S32 CoreRide platform, the S32N55 processor integrates advanced network technology, with a time-sensitive network (TSN) 2.5 Gbit/s Ethernet switch interface, a CAN hub for efficient internal routing of 24 CAN FD buses , 4 CAN XL interfaces and a PCI Express Gen 4 interface, enabling efficient communication and collaboration between various systems in the vehicle.

In addition, the S32N55's "core-to -pin " hardware isolation and virtualization technology enable its resources to be dynamically partitioned to adapt to the ever-changing functional requirements of vehicles. In early 2022, Ambarella released the CV3 series chips with a 5nm process, which can support the development of ADAS and L2+ ~ L4 systems. This series of chips is based on the scalable and energy-efficient CVflow architecture and can achieve 500 eTOPS computing power , which is 42 times higher than Ambarella's previous generation automotive-grade CV2 series. The e in eTOPS refers to equivalent.

Because CVflow is not equivalent to any GPU, the counting unit of CV3 chip AI computing power is different from the TOPS of commonly used GPUs. The addition of e here indicates that it can run at equivalent performance compared with the general chip architecture. Nvidia Orin chip has a computing power of 254TOPS. NIO ET7 achieves 1016 TOPS computing power through 4 Orin cascades. If 4 CV3 chips are cascaded, 2000 eTOPS computing power can be achieved. In February 2023, Ambarella announced that it would use Samsung's 5nm process technology to produce CV3-AD685. Following NXP and Ambarella, Qualcomm 's automotive chips have also begun to adopt 5nm process.

At this point, we have to mention Nvidia and Intel's Mobileye . The smart driving chips of these two companies mostly use 7nm process, while Tesla 's HardWare 3 chip uses Samsung's 14nm process. Not long ago, the supply chain reported that Tesla's new HW4.0 chip will switch to TSMC's 4nm/5nm process. It can be seen that before Weilai, NXP, Ambarella, and Qualcomm all taped out 5nm process automotive chips.

However, there are some differences in the chip types and applications of these companies. From the above introduction, we can see that NXP's S32N55 belongs to the control chip, while Ambarella, Nvidia, Tesla and Weilai are computing chips, and Qualcomm's is a smart cockpit chip, which is more control-oriented. Here we need to briefly introduce the types of automotive chips, which can be divided into computing, control, analog, power , communication , sensor, power, and storage. Among them, computing and control belong to digital chips, which have the highest requirements for process. With the rise of intelligent driving, the requirements for chip computing power are increasing day by day. At this time, the computing power of computing chips has become a very critical indicator, followed by control chips.

In summary, the first companies in the industry to use 5nm process technology to manufacture smart driving chips should be NXP or Ambarella. NIO is the first company in China to use 5nm process technology to manufacture smart driving chips. So why does NIO want to develop such high-end chips on its own? Let's start with NVIDIA. At present, the industry's most used flagship smart driving chip is NVIDIA's Orin-x, which has a single-chip computing power of 508TOPS.

In addition, NVIDIA also released a DRIVE Thor chip with a single-chip computing power of 2000TOPS, which will not be mass-produced until 2025. In 2023, NIO purchased a lot of NVIDIA smart driving chips, accounting for 46% of NVIDIA's shipments, with a total amount of US$300 million. This is a huge expense. For NIO, which has been losing money on research and development, it is necessary to reduce costs and increase efficiency in the increasingly involuted Chinese automobile market . Based on this, it is natural to develop a self-developed smart driving chip. One Shenji NX9031 can replace four NVIDIA Orin Xs, which can save a lot of chip expenses.

02. The value of using 5nm process to manufacture smart driving chips

Traditionally, automotive chips have low requirements for process technology (mostly 20nm or above), but high requirements for chip stability and reliability. In other words, cars need to use automotive grade chips .

Automotive-grade chips are those designed and manufactured for automotive applications and meet stringent automotive industry standards. Such chips need to maintain stable and reliable performance in harsh environments such as extreme temperature ranges, high vibration, high voltage, high humidity, EMI, etc., and usually pass the inspection of automotive industry quality standards such as AEC-Q series certification. Based on the extremely high application requirements of automotive safety and reliability, any chip failure may lead to serious safety accidents. For this reason, compared with consumer-grade or industrial-grade chips, automotive-grade chips have higher quality requirements. Such chips are widely used in vehicle subsystems such as engine control, braking systems, safety systems, in-vehicle entertainment information systems, ADAS, etc. Although advanced processes (16nm and below) can improve chip performance and reduce power consumption , they also bring some challenges. For example, the smaller the process node, the higher the production cost of the chip. In addition, small feature size chips require more sophisticated production equipment and technology, which also increases costs.

Therefore, automotive chip manufacturers and automakers need to find a balance between chip performance, cost and reliability. They need to choose the appropriate process technology according to the purpose, performance requirements and cost budget of the vehicle. For some high-end models, manufacturers may use more advanced processes to improve vehicle performance. For some economical models, manufacturers will choose more economical processes to reduce production costs.

In general, the mainstream process of automotive chips is between 40nm and 16nm. However, with the popularization of intelligent driving, the manufacturing framework of traditional automotive chips has been broken, because computing power has begun to dominate automotive applications. In fact, practitioners know that stacking computing power is bound to lead to waste. However, compared with invisible software algorithms, real computing power indicators can be easily judged.

Users' pursuit of hardware capabilities is fully reflected in mobile electronic products , and now the same situation has continued to smart cars . Based on this, various marketing techniques have appeared in the market. For example, some media compare the computing power level of chips to "house rate", using the difference between dense computing power and sparse computing power to calculate completely different computing power conclusions. Today, volume computing power has become a hurdle that car manufacturers and related chip companies cannot overcome. More and more newly launched smart driving chips have proved that increasing computing power is the most effective way to improve market evaluation.

At present, the computing power of many new SUVs with a price of more than 300,000 yuan has exceeded 100 TOPS, and even the computing power of some brands of cars has exceeded 1,000 TOPS. Even if there is a lot of redundancy, it seems that no one will refuse higher computing power. As the computing power of chips easily exceeds 500 TOPS or even 1,000 TOPS, other indicators of the chip are bound to attract the attention of the public, such as the process technology. Although there is no extreme pursuit of the process for automotive-grade chips, in the field of intelligent driving and smart cockpits, the chip process has obviously begun to advance to 5nm or even smaller process nodes.