Hartley oscillator without coupling inductor

　　If you examine a traditional Hartley oscillator circuit, you will notice its characteristic: a tapped inductor, which determines the oscillation frequency and provides continuous feedback of the oscillation. Although you can easily calculate the total inductance for nominal frequency, solving for the coupling coefficient k may require experimental (i.e., "trial" optimization). This design example introduces an alternative equivalent circuit, allowing you to model the circuit before building a prototype.

　　Figures 1a and 1b show the equivalent tuned circuit of the Hartley oscillator, the formulas for calculating its components, and the component values ​​for an 18MHz oscillator. The mutual inductance is L _M =k√L ₁ ×L ₂ . For the equivalent circuit, the formulas are: L _A =-L _M , L _B = L ₂ -L _A =L ₂ +L _M , L _C =L ₁ -L _A =L ₁ +L _M . The remaining formulas for the equivalent circuit are:

　　　　　　　　　　　　　　　　　　　and

　　Unfortunately, a truly equivalent circuit requires a negative inductance L _A . However, for frequencies near the resonant frequency f0 _, this negative inductor can be replaced by a capacitor, CA _instead of LA ₍ Fig. 1c). Please note: The equivalent circuit solution ignores parasitic winding resistance and capacitance.

　　Figure 2 depicts an oscillator-cum-output buffer utilizing the equivalent circuit. The circuit you built performs roughly as you would expect from your initial Spice simulation. During testing, the values ​​of several components needed to be adjusted, and multiple iterations of Spice analysis resulted in the final design. The oscillator's oscillating circuit consists of LB _, LC _, C4 _and C5 _, plus the capacitance provided by the voltage divider _C6 , _C7 and C8 _. This approximately 6 pF capacitor contains the input capacitance of Q ₁ and Q ₂ and some stray capacitance. The total oscillation capacitance of 66 pF is close to the calculated value of 67 pF. Individual capacitors connected to the tuned circuit have ceramic dielectric construction and NP0 temperature coefficient.

　　Inductors LB _and LC _consist of air-core coils with their axes perpendicular to each other to minimize parasitic coupling. However, vibration will affect their inductance, and in the final design both should consist of windings on a dielectric or toroidal core, provided that the inductance temperature coefficient of the toroidal core is acceptable for the intended application. Reference 1 provides a basic design of two inductors, and by adjusting the spacing of their turns, the oscillator can be tuned to exactly 18 MHz. For more rigorous designs, individual inductors can be measured prior to installation, but parasitic effects may require re-adjustment of individual inductor values.

　　A capacitive voltage divider consisting of C ₆ , C ₇ and C ₈ applies the appropriate signal levels to Q ₁ and Q ₂ . Since the voltage divider "sees" the effective capacitance of the tank as only 6 pF, the remaining 60 pF can form a variable capacitor if the design requires a tunable oscillator. In this example, if the oscillator requires a tuning range beyond ±2 MHz, the output stage consisting of Q3 _and its associated components will need to be modified to provide greater bandwidth.

　　Capacitor C _bootstraps Q ₁ 's Gate2 to the source of Q _{1 to provide additional gain from Q 1} and reduces its Gate1 input capacitance below a value of approximately 2.1 pF (Reference 2). The 8.3mH inductor L2 _is connected to the source of Q1 _and presents a higher impedance at 18 MHz, providing a DC path from the source of Q1 to ground _{through R3 .} The impedance of L ₂ at 18 MHz consists of an inductive reactance of about 940Ω in parallel with a resistor of about 3.5 kΩ, which results in a choke with low resistive losses. _{L 2} can be replaced with a smaller inductor , provided its inductance and reactance are close to the original values. An 8.2mH choke with standard values ​​can be used as L2 _, provided that its resistive losses comply with these low-loss guidelines and that its inherent series resistance does not exceed 2Ω to avoid disturbing the DC bias voltage of _{Q1 .} The inductance and resonance of the choke for L are less critical than those for L _, but using a choke with low resistive losses in L _can help avoid parasitic resonances _. 　　Source follower Q2 _drives the output stage, which uses a pi matching network to convert the 50Ω output load into 285Ω at the collector of _{Q3 .} Boosting Q _'s Gate2 at half its output voltage increases the source follower's gain and dynamic range and reduces its input capacitance. Potentiometer R ₅ adjusts the output level of this circuit from about 0.9V pp to about 1.5V pp on a 50Ω load. The frequency of the circuit remains stable at a constant room temperature of approximately 23°C. Additionally, the output level control circuit remains stable even when no load is applied to the output. For a fixed frequency oscillator, a load resistor loss of approximately 4 in the output circuit provides sufficient bandwidth without retuning L ₃ , C ₁₆ , and C _{17 .} 　　To set the output level at a safe maximum value, connect a 50Ω load to the output and regulate the output to 1.5V pp. _{The drain-to-source voltage applied to Q1} remains at a safe level for all loads from zero load to 50Ω, even as the output voltage level increases with the load resistance . To avoid exceeding the maximum 12V drain-to-source voltage specified for Q1, the output voltage setting into a 50Ω load should not exceed 1.5V _. Please note: Zener diode D _reduces Q _'s drain voltage to provide additional safety margin. 　　In the previous design example, an op amp and diode rectifier circuit controlled the oscillator gain by applying a variable voltage to Gate2 of Q ₁ (Reference 3). In this design, a simple passive circuit serves the same purpose. Part of the Q ₃ collector signal drives a voltage multiplier consisting of D ₂ , D ₃ , C ₂₀ and C _{21 .} The voltage multiplier produces a negative voltage, part of which drives the junction of R ₁₈ and C _{19 , the control voltage node.} This control voltage node also receives a positive voltage from variable resistor R _{15 through R 17} and the resulting voltage sets the output signal level. At startup, there is only a positive voltage present at Gate2 of Q1 _, and the maximum gain of Q1 _easily starts the oscillator. When the output reaches a steady state, the control voltage decreases to maintain the oscillation at the signal level determined by the output level control value.

References
1. Reed, Dana G, Editor, "Calculating Practical Inductors," ARRL Handbook for Radio Communications, 82nd Edition, American Radio Relay League, 2005, pg 4.32.
2. "Practical FET Cascode Circuits," Designing with Field-Effect Transistors," pg 79, Siliconix, 1981.
3. McLucas, Jim, "Stable, 18-MHz oscillator features automatic level control, clean-sine-wave output," EDN, June 23, 2005, pg 82, www.edn. com/article/CA608156 .