In the 2008 Zhejiang Province College Students
Electronic
Design Competition, there was a topic called "Music Player Design", which required playing music with 12 keyboards. One of the technical indicators for the scale required a frequency error of less than ±0.1%. The key to this topic is to generate a high-precision sound source. The commonly used
method of generating signals by using
a single-chip
microcomputer timer interrupt can barely meet this requirement. This topic has an attached table of scale corresponding frequencies, which describes the exact values of the corresponding frequencies of each scale. For example, the frequency of scale 6 is 739.99 Hz, and the 51 series
single-chip
microcomputer timer interrupt method cannot meet the frequency accuracy requirements described in the table data. However, the use of DDS technology can meet this frequency accuracy requirement. Compared with the signal generated by the 51 single-chip microcomputer timer, the scale signal generated by DDS has the advantage of high frequency accuracy and produces a sine wave with the characteristics of "pure" sound, which has a better auditory effect. Based on the above reasons, the use of DDS+MCU is a better design solution for realizing a music player. Its technical core is the generation of controllable scales, which constitutes a sound source generator. The sound source generator introduced in this article can be used for tuning the piano and has certain practical value.
1 Principle of sound source generation
Tierney J, Tader CM and others first proposed the concept of DDS or DDFS (Direct Digital Frequency Synthesis) in 1971. DDS is usually regarded as the third generation of frequency synthesis technology. DDS breaks through the principle of previous frequency synthesis methods and performs frequency synthesis based on the concept of "phase". This method can not only generate sine waves of different frequencies, but also
control
the initial phase of the waveform. In addition, the DDS method can be used to generate arbitrary waveforms (AWG).
The basic structure of DDS is shown in Figure 1, including the main frequency, synchronous adder, frequency word register, ROM, D/A, LPF, etc. The main frequency generates the main clock, and the synchronous adder performs synchronous addition according to the main clock. One addend of the synchronous adder is the frequency word stored in the frequency word register, and the other addend is the result of the last addition operation (sum) of the synchronous adder. The addition result (sum) of the synchronous adder is used as the address of the ROM, which stores the waveform data. The data output of the ROM is converted into
an
analog
quantity by D/A, filtered by LPF, and then output as the waveform stored in the ROM.
For a basic DDS chip, the main frequency f
MCLK
= 1 MHz, the frequency word FREQREG = 1, and the number of bits of the synchronous adder is 8, then the synchronous adder is equivalent to a counting process of 0 to 255 (0x00 to 0xFF), which is repeated cyclically, and its cycle frequency is fMCLK/256. If the ROM stores sinusoidal wave data, after D/A conversion and LPF filtering, the output frequency is a sinusoidal wave signal of f
MCLK
/256; when the frequency word FREQREG = 2, the synchronous adder is equivalent to an accumulation process of 0 to 255 (0x00 to 0xFF) with a step length of 2, and the frequency of this process is 2×f
MCLK
/256, that is, the output frequency is 2×f
MCLK
/256. Sine wave signal.
By analogy, the output frequency of the basic DDS chip is:
f
0
=f
MCLK
/2
8
×FREQREG
For the basic DDS chip, the main frequency f
MCLK
is generally generated
by the crystal oscillator
circuit
and is relatively fixed. Therefore, the output frequency of the DDS depends on the frequency word, which is generally
set
through a serial or parallel
interface
.
The change interval (resolution) of the output frequency of the DDS chip is f
MCLK
/2
8
(when the number of bits of the synchronous adder is 8). The stability of the output frequency mainly depends on the stability of the crystal oscillator, and the output waveform depends on the waveform data in the ROM. According to the Nyquist theorem, the maximum output frequency is less than f
MCLK
/2.
Since the result of the synchronous adder is to change the phase of the output waveform, in the information about DDS chips [1], the synchronous adder is usually called a phase accumulator.
In actual application, the structure of DDS will be much more complicated. The number of bits of the synchronous adder is much larger than 8. With the addition of the phase adder, the ROM and D/A data width will be more than 10 bits, and the main frequency will also be higher. Therefore, dedicated chips are usually used, and a small number of them are implemented using
FPGA
(especially when AWG needs to be implemented).
Qualcomm, Analog Devices, and other companies have launched a series of DDS dedicated chips. Typical ones include AD9850, AD9851, AD9852, AD9853, AD9833, etc. Current signal generators widely use DDS dedicated chips as the circuit core [1]. The college electronic competitions over the years have all involved questions about the application of DDS chips.
AD9833 is a low-power, programmable waveform generator produced by Analog Devices that can generate sine wave, triangle wave, and square wave outputs. The output frequency and phase can be programmed by software, making it easy to adjust. It uses a 28-bit frequency register. When the main clock is 25 MHz, the frequency resolution is 0.1 Hz; when the main clock is 1 MHz, the frequency resolution can reach 0.004 Hz [2].
AD9833 adopts 10-pin MSOP package and uses SPI interface to set control register and frequency register. It has simple functions and is easy to use. Therefore, AD9833 chip is selected as the scale frequency generator. The pin diagram of AD9833 chip is shown in Figure 2.
Under the condition of suitable main frequency, the ideal signal output can be obtained by setting the frequency register and control register through the SPI interface. Its output frequency is:
2 Hardware Design
The AD9833 chip has 3 serial interface lines, which are compatible with SPI, QSPI, MI-CROWIRE and DSP interface standards. Under the action of the serial port clock SCLK, the data is loaded to the device in 16-bit mode. Its timing diagram is shown in Figure 3. The FSYNC pin is an enable pin, level-triggered mode, and low level is effective. When performing serial data transmission, the FSYNC pin must be set low.
In this design, MCU uses 51 series chips. Figure 4 is the circuit schematic of the sound source. P1.5, P1.6, and P1.7 are connected to FSYN, SCLK, and SDA of the AD9833 chip respectively. The MCU sets the registers of the AD9833 chip by simulating the timing of SPI. Y2 is an active crystal oscillator. Its third pin outputs a signal with a frequency of 4.194 304 MHz, which is provided to the main frequency input terminal of the AD9833 chip. The signal generated by the AD9833 chip is output through JP3 and connected to the audio power amplifier circuit. The audio power amplifier drives the speaker to sound.
3 Software Implementation
In this design, the main frequency clock is 4.194 304 MHz. The output frequency is calculated as follows:
Where f0
is
the output frequency, fMCLK
is
the main frequency (4.194 304 MHz), and FREQREG is the frequency word set by the frequency register. The frequency resolution is 1/64=0.015 625 Hz.
According to the above formula, the frequency word parameters corresponding to each scale are calculated as shown in Table 1.
The control program is developed in the Keil uv2 environment, and the program is implemented in a mixed programming form of assembly language and C language. The timing control part is implemented in assembly language, and the main part is programmed in C language. When the main part of the program calls the timing control part, data is passed through the global byte variables light_o and light_o1.
The timing control program completes the setting of the internal registers of the DDS chip by simulating the SPI interface timing. The specific program is as follows (the definition part is omitted):
to_9833:
setb SCK
clr CS
mov a,light_o
mov r1,#08h
call out_SPI
mov a,light_o1
mov r1,#08h
call out_SPI
setb CS
clr SCK
ret
out_SPI:
RLC A
mov SO,c
clr SCK
setb SCK
djnz r1,out_SPI
ret
In the main part of the program, the scale data is defined as a one-dimensional array according to Table 1:
code unsigned int music_table[ ]={0x5268,0x5c80,
0x67d3, 0x6e00, 0x7b78, 0x8a97, 0x92d5, 0xa4d5, 0xb8ff, 0xcfa7, 0xdc00, 0xf6f0,};
The main program block diagram is shown in Figure 5. The AD9833 chip is initialized by writing the control word. The program runs in the main loop. The main loop processes the valid keys, and for the valid keys, the scale function is called. The scale function is as follows:
void play_music(unsigned char nn)
{
light_o = 0x20;
light_o1 = 0x00; //Set the control word
to_9833();
v_3.cm_int = music_table[nn]; //Look up the scale table
light_o = 0x40 | (v_3.cm.cm_0 & 0x3f);
light_o1 = v_3.cm.cm_1;
to_9833(); //Set the frequency word
light_o = 0x40;
light_o1 = v_3.cm.cm_0 / 0x40;
to_9833();
}
If a key of scale 2 is pressed, the C language description of the calling function is:
play_music(2);
The program also includes key processing, display, storage control and other parts, which are not described in detail due to space limitations. After actual measurement, the frequencies of each scale generated by this sound source generator are consistent with the design values in Table 1, the frequency error is <0.02%, and the waveform is a "pure" sine wave. Through power amplification, the speaker is driven to produce sound.
Usually, different musical instruments have harmonics with different characteristics when they sound. It is difficult for conventional musical instruments to achieve a scale with only the main tone and no harmonic components. The sound source designed by the DDS chip in this article has achieved an accurate scale without harmonic components, which has a unique auditory effect. It can be used as a reference scale for tuning various musical instruments.
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