Ultra-low frequency sawtooth wave generating circuit composed of common components

Function of the circuit

When it comes to sawtooth waves, people will immediately think of Miller integrator circuits composed of OP amplifiers or discrete components. However, the ultra-low frequency sawtooth wave generation circuit with a long period will cause linear deterioration due to the influence of factors such as the input bias current of the OP amplifier or the insulation resistance of the integral capacitor. To solve this problem, counters and DA converters can be used to make the time period unlimited. However, if the output waveform is amplified, it will appear step-like. In order to make the waveform look like a straight line, the multiple of the DA converter should be relatively large, and the specific number of bits can be determined according to the application purpose.

This circuit can achieve the same purpose without using a DA converter IC, thus reducing the cost.

How the Circuit Works

This circuit consists of clock oscillator IC1, 10-bit counter IC2, R-2R ladder network, reference voltage generator IC2, buffer amplifier A1, etc. The clock oscillator uses an unstable multiplier of C-MOS gate circuit, which is suitable for low-frequency oscillation. If the multiple of the counter is assumed to be N, the required oscillation frequency F is F=2NF=1024FO. First, select the appropriate capacity of C1, and then use the formula R3+VR1=1/2.2F.C1 to calculate the oscillation frequency. VR1 must make the oscillation frequency have an adjustment range of ±20%, which is due to the threshold voltage of C-MOS IC or the error of capacitor C1. A hold output terminal is added to the circuit, so that the oscillation can be stopped at any time. The counter IC is a C-MOS binary counter, and increasing the number of bits can generate a high-precision sawtooth wave. The output voltages VOH and VOL of C-MOS IC are roughly equal to VDD and VSS, but the additional current must be reduced, so the resistance values ​​of the R-2R ladder resistor network are 75K and 150K, which are relatively high.

If VDD cannot be stabilized, the amplitude of the sawtooth wave will change, and a three-terminal regulator must be used to stabilize the power supply of the C-MOS circuit.

The output resistance of the ladder resistor network is relatively large, 75K, so buffer amplifier A1 must be used to obtain an amplitude of 10V, and the gain is set to 2.

The output waveform is a step wave that divides the voltage of 0~10V into 1024 equal parts. When the frequency remains unchanged, adding capacitor C3 can extend the rise time and obtain a smooth waveform C3≈1/2 (2/πF*75*10 to the power of 3).

Adjustment

Set the sawtooth wave period to 100 seconds, and the clock frequency to 1024*0.01=10.24HZ. The frequency is low, and it is difficult to detect the entire circuit. It is best to detect it at a high frequency. If there is a frequency counter, the clock output can be directly calculated.

VR2 is the offset adjustment potentiometer, which is used to adjust the output of A1 so that its output is 0 when the counter is reset.

The output amplitude is determined by the voltage of the 3-terminal regulator. To adjust it accurately, a 1K variable resistor can be connected in parallel with the feedback resistor R5.