How to use existing layout to eliminate snubber/inverter

In SoC design, the logic inserted after the EDA tool processes the netlist is called ECO. The entire SoC design cycle of synthesis, place and route, extraction, crosstalk, etc. can be avoided, thus saving time to complete ECO. Post-mask engineering change lists can be performed in a cost-effective manner. If a change can be completed by modifying only a few metal layers, the cost involved is much less than completely redoing the entire design. ECOs usually use spare gate blocks (inserted during synthesis). Typically, these spare gate blocks include NAND, NOR, flip-flops, buffers, inverters, and other logic cells that may be used. This article focuses on how to use the buffer/inverter (pair) logic of the existing layout and use spare cell blocks to avoid violating the design (DRV) rules.

introduce

Implementing an Engineering Change Order (ECO) is a very common step in the System-on-Chip (SoC) design phase. There are many reasons for using ECOs in a design.

1. Pre-planned ECO: Sometimes, designers can pre-set the use of ECO. For example, sometimes there may be a situation where IP needs to be introduced in the late stage of the ASIC design cycle, so designers should plan their activities appropriately to avoid being restricted in the design stage. However, it is said that the use of ECO in the design cycle is mostly accidental.

2. Functional modifications: ECO may also be the result of functional modifications required by the design specifications. If the customer requires additional functions or the application software requires the hardware to deploy this function, such modifications may be required.

3. Design issues: Design issues may appear in the silicon results of some previous test chips in gate level simulation (GLS) or similar techniques.

To implement ECO in logic gates, designers need an optimal solution because adding additional gates may cause the base layer (such as activation layer, polysilicon layer, nitride layer) masks to be remanufactured, which is much more expensive than the interconnect mask. Therefore, ideally, designers would like to include only logic that uses existing logic to reduce the cost of remanufacturing.

Problem Statement:

Using additional logic gates to include an ECO can impact the overall timing and routability of the design. Specifically, when the ECO logic is large enough, the impact on module implementation density can reach 100%.

Current methods:

The current solution to this problem is to add extra gates within each module during the physical synthesis phase of the design, so when ECO is performed, the existing spare gates can be used later to include the changes in the design. This avoids having to add more logic. However, this approach has certain limitations.

Limitations of current methods:

1. Designers cannot predict the optimal number of spare gates for a module to avoid ECO abort; for example, suppose a functional ECO needs to connect 10 buffers in a chain. But the existing spare cell module has only 6 buffers, and we have to re-spin the SoC because there is no buffer/inverter (pair). Basically, this limitation means that designers have to put more redundant logic in one module or spare limited spare gates in another module.

2. An oversized ECO will inevitably violate hold time and violate design rules, such as violating the maximum transition or maximum drive strength of logic gates. This requires additional redundant buffers to solve hold time violations or improve the slew rate performance of signals that are prone to DRV.

Suggested solutions:

This article wants to introduce a solution where we can use the existing layout to eliminate the snubber/inverter (pair).

Keep in mind that in spare scale blocks, you may have to add redundant NAND/NOR gates and extra flip-flops/latches, but you don't necessarily need to add redundant buffers and inverters.

Basically, this paper attempts to demonstrate an innovative approach that uses optimization techniques to recover the buffer/inverter logic from an existing layout.

Algorithms and Pseudocode

Figure 1: Basic algorithm to be implemented for a window size of (x1,y1,x2,y2)

Pseudo code to generate window size:

beginning

x=x1;y=y1;

When x < x2,

When y < y2

x' = x + a, y' = y + b;

x=x',y=y'

If x > x2 or y > y2

x=x2, y="y2";

Finish

Each window coordinate generated is represented by (x, y, x', y')

Here a and b need to be determined according to the specific design and technology. If the SoG (Sea of ​​Gates) area of ​​the SoC is 7 mm2 or larger, designers need to pay attention to the complexity of the calculation when calculating the window size.

describe:

As shown in the flowchart above, the core of the idea is how to identify non-critical buffers (wrt timing margin). When implementing ECO, we inevitably need to use buffers of spare cell modules. Now, the placement of this buffer is more arbitrary, and using it will violate the DRV rules.

For example, let's assume that BUFX8 is used to drive 5 fanouts. The total capacitance load (including lines and pins) is 200fF. Now according to the SPICE characteristics of this buffer, any load above 150fF will result in poor output slew. Poor output slew will not only violate the maximum transition value, but also affect the timing of the fanout driver circuit.

Therefore, in this case, it is wise to follow the algorithm above, which allows us to do the following steps:

1. Find the target point of ECO: We should find the start and end point positions, which are the positions where the snubber components are placed. This position determines the window size, in which we should search for non-critical snubber/inverter (pair).

2. Decide on the window size: This is entirely up to the designer. He can choose the window size based on the technology. If the maximum load that the buffer can drive is 200fF, then the window size should be modified accordingly.

3. Identification of buffer/inverter (pairs): Now, the algorithm will run on a specific window and try to identify all buffer/inverter (pairs) present in the marked positions.

4. Calculate timing margin: Once the buffer/inverter pair is marked, the algorithm should try to find the timing margin with these standard cells. If these standard cells are critical to timing, then the buffer/inverter pair does not need to be marked. As long as the buffer/inverter pair remains marked, then removing either one will not affect the existing timing of the design.

5. Final step: Now the marked buffer/inverter (pair) is ready for ECO.

in conclusion

Layout optimization and the use of redundant cells can help designers digest complex ECOs in the later design phase of multi-million-gate SOCs while avoiding impact on the overall product's time to market.